Translation entries from regimes with no ASID support are
tagged as global.
For complete translations we cannot simply check for the EL
being EL2 or EL3 as the EL2&0 translation regime does support
ASIDs to differentiate userspace host applications.
We therefore change the LongDescriptor::global method to cover
the EL2&0 case.
We also fix the partial translation logic which was labelling
partial translations as non global without checking for the
translation regime
Change-Id: I9375a34eba6ede97d70ed80e43ce363a57678d55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62452
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The description explains when we have to set this True (when a
downstream cache acts as a victim cache). Also, it describes general
(default) setup, but this seems inaccurate and not consistent with
default vaule.
Change-Id: I389adb0af0d6421e8a9672c4cf5d23510eb38242
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62832
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
By default, caches in classic memory system are assume to be a mostly
inclusive cache with respect to their upstream caches.
Therefore, `writeback_clean` should be `False` by default, which is
consistent with src/mem/cache/Cache.py
Change-Id: I1395690f7f5fafee7fb151906302877ada953861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit adds the concept of a "Workload" to the stdlib. Workloads
specify the details needed to run a particular gem5 workload on an
stdlib board. These are specified as part of gem5-resources and loaded
via the `Workload` class though can be specified locally via the
`CustomWorkload` class.
Tests are included in this commit to verify the functionality of these
Workloads.
Change-Id: I8840d281eb01ee4138f01ee499cae96bf7e0579d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62532
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This change adds a component for HBM2 stack in the gem5 stdlib.
For HBM2 stack, the atom size is used to interleave across pseudo
channels in a single physical channel or HBMCtrl and the bits
beyond that will be used to interleave across channels/controllers.
Change-Id: I95a279504981a5c000f38c9a6ad0e03484eb258e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This change adds a flag to MemCtrl to allow disabling
response port's queue size sanity check. This is needed
for cases/tests where you might want to drive the memory
system with a much higher bandwidth, for example as in
HBM2.
Change-Id: If8d621339ce8f3ab92cbe2b94039486705c64fc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62372
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
An exception was raised if the SwitchableProcessor was setup to
switch to a KVM core from a non-KVM core (i.e., if KVM cores were
present they needed to be the starting core). This was due to a bug in
the Simulator module where the `root.sim_quantum` as not setup for cases
where the SwitchableProcessor was not starting with a KVM core, thus
causing an error when switched to KVM cores.
This has been fixed by modifying the Simulator module to always set
root.sim_quantum. This is acceptable as this is only used in KVM setups.
Change-Id: If57352ba67b7bca81882eae2ef1e9013ef45272f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62471
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Without setting the correct memory mode the SimpleSwitchableProcessor,
the Minor CPU could not be used as a valid core. This patch corrects
this issue by setting the memory mode to TIMING for Minor CPU cores.
Due to the increasingly complex if-else to determine the memory mode, a
function has been added to CPUTypes to determine what MemMode is
required for each CPUType.
Change-Id: I9384b4a9c0673af34cca04917d763ca45d0ea434
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61535
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
The `set_se_binary_workload` function was only setting up the binary to
work on one (the first) processor core. This caused an exception to be
thrown when trying to run an SE mode binary on a multicore system.
Tests have been added to ensure this works as intended.
Note: While this implementation fixes the bugs, it is limited. Future
work is needed to allow for multiprogram workloads.
Change-Id: I33dbaf5015705c299215dc83e8449b16df301cd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62014
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Currently, when using the switchable processor the first N cores are the
starting cores and the next N cores (e.g., board.processor.core<N+1>)
are the switched in cores. This is confusing when looking at the stats.
This change makes it so that the names of the different processor lists
used in the dictionary when constructing the switchable processor are
used in for the member names as well. This will allow users to have
names like board.processor.ff_cores and board.processor.detailed_cores.
A bit of refactoring of the base processor was required for this.
Change-Id: I244ee5f6080599acb60a777da979da048cf7463e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
In commit 83b14e56, getVirtProxy is replaced by inline ternary operators
to decide between FS or SE version. However, dynamic dispatch will not
work in this scenario and the virtual function of SETranslatingPortProxy
will not be called. It may lead to failure in m5op read_file in SE mode.
Change-Id: I9b5f757096cfdbd6fb8bc14b1b0e02245703a0ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62611
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
The current MI_example protocol's L1 caches updates the MRU information twice per request on misses -- once when the request reaches Ruby and once when the miss is returned from another level of the memory hierarchy.
Although this approach does not cause any correctness bugs for replacement policies like LRU since this request is the LRU in both cases, it does not work correctly for other policies like SecondChance and LFU, where updating the information twice (for misses) causes them to devolve to LRU.
Note that this was not directly a problem with Ruby previously, because it only supported LRU-based policies that were unaffected by this. However, with the integration of 20879 Ruby now uses the same replacement policies as Classic (which has additional, non-LRU based replacement policies).
This patch resolves this problem by not updating the MRU information a second time for the misses. It has been tested and validated with the replacement policy tests in 20880.
Change-Id: I82a57abf2a16d70820413ba8118378f2e91fd7fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62232
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
BasicDecode, or decode block templates in general, contains the template
for substituting the return statement returning a StaticInst given a
machine code.
In the case of micro-coding an instruction, this return statement is for
the macro op. Additionally, in gem5 riscv, the spawned micro-ops will be
added in the macro op constructor, which is done in the macro-op
constructor template. Thus, there's no need for having a return statement
for the micro-op.
Currently, there are two return statements in decode-method.cc.inc for
each riscv atomic inst. This change removes one of the two BasicDecode
blocks in atomic inst templates.
This change is expected to a cosmetic change.
Change-Id: Id14bde25d5d3f164b4faafd33bfd5c802a94ca09
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62492
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The BaseCPUProcessor is processor containing BaseCPUCores. This gives
gem5 stdlib users a way to create processors containing BaseCPU
SimObjects. While SimpleProcessor does this by-proxy (the user simply
specifies the desires CPUType and ISA and the correct BaseCPU
instantiation is chosen), this new Processor allows a more raw passing
of BaseCPU objects.
The SimpleProcessor now inherrits from this BaseCPUProcessor to avoid
duplcation of functionality. A refactor to achieve this was moving the
setting of the board's memory mode from the SimpleProcessor's
"incorporate_processor" function to the BaseCPUProcessor's then altering
it to determine MemMode based on BaseCPU subclass rather than the
CPUType.
The tests/gem5/configs/simple_binary_run.py test script has been
extended to create an stdlib run with a BaseCPUProcessor instead of the
SimpleProcessor and tests have been included to ensure the
BaseCPUProcessor functions as intended.
Multiple cores comprising of different BaseCPU types has not been tested
and is not officially supported as of this commit.
Change-Id: I229943ab98ece39646f1b4feb909250bb5c61772
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62353
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This is the last part needed needed to deprecate SimpleCore's
"get_type" function. This "requires_send_evicts" function can be used by
the cache hierarchy to determine whether the core requres sending
evictions from caches.
Change-Id: I4e42d9fcecf0b1c4344f4cd145126a2ea57b7b76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62352
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
