stdlib: Add "requires_send_evicts" function to AbstractCore

This is the last part needed needed to deprecate SimpleCore's
"get_type" function. This "requires_send_evicts" function can be used by
the cache hierarchy to determine whether the core requres sending
evictions from caches.

Change-Id: I4e42d9fcecf0b1c4344f4cd145126a2ea57b7b76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62352
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

@@ -89,21 +89,10 @@ class AbstractNode(Cache_Controller):
 
     def getBlockSizeBits(self):
         bits = int(math.log(self._cache_line_size, 2))
-        if 2 ** bits != self._cache_line_size.value:
+        if 2**bits != self._cache_line_size.value:
             raise Exception("Cache line size not a power of 2!")
         return bits
 
-    def sendEvicts(self, core: AbstractCore, target_isa: ISA):
-        """True if the CPU model or ISA requires sending evictions from caches
-        to the CPU. Scenarios warrant forwarding evictions to the CPU:
-        1. The O3 model must keep the LSQ coherent with the caches
-        2. The x86 mwait instruction is built on top of coherence
-        3. The local exclusive monitor in ARM systems
-        """
-        if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86, ISA.ARM):
-            return True
-        return False
-
     def connectQueues(self, network: RubyNetwork):
         """Connect all of the queues for this controller.
         This may be extended in subclasses.

src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

@@ -50,7 +50,7 @@ class PrivateL1MOESICache(AbstractNode):
         )
 
         self.clk_domain = clk_domain
-        self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa)
+        self.send_evictions = core.requires_send_evicts()
         self.use_prefetcher = False
 
         # Only applies to home nodes

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py

@@ -55,21 +55,10 @@ class AbstractL1Cache(L1Cache_Controller):
 
     def getBlockSizeBits(self):
         bits = int(math.log(self._cache_line_size, 2))
-        if 2 ** bits != self._cache_line_size.value:
+        if 2**bits != self._cache_line_size.value:
             raise Exception("Cache line size not a power of 2!")
         return bits
 
-    def sendEvicts(self, core: AbstractCore, target_isa: ISA):
-        """True if the CPU model or ISA requires sending evictions from caches
-        to the CPU. Two scenarios warrant forwarding evictions to the CPU:
-        1. The O3 model must keep the LSQ coherent with the caches
-        2. The x86 mwait instruction is built on top of coherence
-        3. The local exclusive monitor in ARM systems
-        """
-        if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86, ISA.ARM):
-            return True
-        return False
-
     @abstractmethod
     def connectQueues(self, network):
         """Connect all of the queues for this controller."""

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py

@@ -69,7 +69,7 @@ class L1Cache(AbstractL1Cache):
         self.l2_select_num_bits = int(math.log(num_l2Caches, 2))
         self.clk_domain = clk_domain
         self.prefetcher = RubyPrefetcher()
-        self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa)
+        self.send_evictions = core.requires_send_evicts()
         self.transitions_per_cycle = 4
         self.enable_prefetch = False
 

src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py

@@ -50,7 +50,7 @@ class L1Cache(AbstractL1Cache):
         )
 
         self.clk_domain = clk_domain
-        self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa)
+        self.send_evictions = core.requires_send_evicts()
 
     @overrides(AbstractL1Cache)
     def connectQueues(self, network):

src/python/gem5/components/processors/abstract_core.py

@@ -42,6 +42,16 @@ class AbstractCore(SubSystem):
     def get_isa(self) -> ISA:
         raise NotImplementedError
 
+    @abstractmethod
+    def requires_send_evicts(self) -> bool:
+        """True if the CPU model or ISA requires sending evictions from caches
+        to the CPU. Scenarios warrant forwarding evictions to the CPU:
+        1. The O3 model must keep the LSQ coherent with the caches
+        2. The x86 mwait instruction is built on top of coherence
+        3. The local exclusive monitor in ARM systems
+        """
+        return False
+
     @abstractmethod
     def is_kvm_core(self) -> bool:
         """

src/python/gem5/components/processors/base_cpu_core.py

@@ -59,6 +59,30 @@ class BaseCPUCore(AbstractCore):
     def get_simobject(self) -> BaseCPU:
         return self.core
 
+    @overrides(AbstractCore)
+    def requires_send_evicts(self) -> bool:
+        if self.get_isa() in (ISA.ARM, ISA.X86):
+            # * The x86 `mwait`` instruction is built on top of coherence,
+            #   therefore evictions must be sent from cache to the CPU Core.
+            #
+            # * The local exclusive monitor in ARM systems requires the sending
+            #    of evictions from cache to the CPU Core.
+            return True
+
+        # The O3 model must keep the LSQ coherent with the caches.
+        # The code below will check to see if the current base CPU is of the O3
+        # type for the current ISA target (a bit ugly but it works).
+
+        try:
+            from m5.objects import BaseO3CPU
+
+            return isinstance(self.get_simobject(), BaseO3CPU)
+        except ImportError:
+            # If, for whatever reason, the BaseO3CPU is not importable, then
+            # the current core cannot be an an O3 CPU. We therefore return
+            # False.
+            return False
+
     @overrides(AbstractCore)
     def is_kvm_core(self) -> bool: