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arch: Remove unused register flattening methods.

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Most flattening methods in the ISA classes aren't used. The one
exception is the flattenMiscIndex function in ARM.

Change-Id: I26088692fe3f56914009afb0203f59da7cf6023a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51235
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-10-01 06:29:07 -07:00
parent eaa67ca1ab
commit d130fdc092
6 changed files with 0 additions and 226 deletions
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91
src/arch/arm/isa.hh
View File

@@ -198,97 +198,6 @@ namespace ArmISA
void setMiscRegNoEffect(int misc_reg, RegVal val);
void setMiscReg(int misc_reg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
{
switch (regId.classValue()) {
case IntRegClass:
return intRegClass[flattenIntIndex(regId.index())];
case FloatRegClass:
panic("ARM doesn't use FloatRegClass.");
case VecRegClass:
return vecRegClass[flattenVecIndex(regId.index())];
case VecElemClass:
return vecElemClass[flattenVecElemIndex(regId.index())];
case VecPredRegClass:
return vecPredRegClass[flattenVecPredIndex(regId.index())];
case CCRegClass:
return ccRegClass[flattenCCIndex(regId.index())];
case MiscRegClass:
return miscRegClass[flattenMiscIndex(regId.index())];
case InvalidRegClass:
return RegId();
}
panic("Unrecognized register class %d.", regId.classValue());
}
int
flattenIntIndex(int reg) const
{
assert(reg >= 0);
if (reg < int_reg::NumArchRegs) {
return intRegMap[reg];
} else if (reg < int_reg::NumRegs) {
return reg;
} else if (reg == int_reg::Spx) {
CPSR cpsr = miscRegs[MISCREG_CPSR];
ExceptionLevel el = opModeToEL(
(OperatingMode) (uint8_t) cpsr.mode);
if (!cpsr.sp && el != EL0)
return int_reg::Sp0;
switch (el) {
case EL3:
return int_reg::Sp3;
case EL2:
return int_reg::Sp2;
case EL1:
return int_reg::Sp1;
case EL0:
return int_reg::Sp0;
default:
panic("Invalid exception level");
return 0; // Never happens.
}
} else {
return flattenIntRegModeIndex(reg);
}
}
int
flattenFloatIndex(int reg) const
{
assert(reg >= 0);
return reg;
}
int
flattenVecIndex(int reg) const
{
assert(reg >= 0);
return reg;
}
int
flattenVecElemIndex(int reg) const
{
assert(reg >= 0);
return reg;
}
int
flattenVecPredIndex(int reg) const
{
assert(reg >= 0);
return reg;
}
int
flattenCCIndex(int reg) const
{
assert(reg >= 0);
return reg;
}
int
flattenMiscIndex(int reg) const
{

11
src/arch/mips/isa.hh
View File

@@ -142,17 +142,6 @@ namespace MipsISA
public:
ISA(const Params &p);
RegId flattenRegId(const RegId& regId) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }
int flattenFloatIndex(int reg) const { return reg; }
int flattenVecIndex(int reg) const { return reg; }
int flattenVecElemIndex(int reg) const { return reg; }
int flattenVecPredIndex(int reg) const { return reg; }
// dummy
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
bool
inUserMode() const override
{

45
src/arch/power/isa.hh
View File

@@ -92,51 +92,6 @@ class ISA : public BaseISA
fatal("Power does not currently have any misc regs defined\n");
}
RegId flattenRegId(const RegId& regId) const { return regId; }
int
flattenIntIndex(int reg) const
{
return reg;
}
int
flattenFloatIndex(int reg) const
{
return reg;
}
int
flattenVecIndex(int reg) const
{
return reg;
}
int
flattenVecElemIndex(int reg) const
{
return reg;
}
int
flattenVecPredIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg) const
{
return reg;
}
bool
inUserMode() const override
{

9
src/arch/riscv/isa.hh
View File

@@ -89,15 +89,6 @@ class ISA : public BaseISA
void setMiscRegNoEffect(int misc_reg, RegVal val);
void setMiscReg(int misc_reg, RegVal val);
RegId flattenRegId(const RegId &regId) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }
int flattenFloatIndex(int reg) const { return reg; }
int flattenVecIndex(int reg) const { return reg; }
int flattenVecElemIndex(int reg) const { return reg; }
int flattenVecPredIndex(int reg) const { return reg; }
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
bool inUserMode() const override;
void copyRegsFrom(ThreadContext *src) override;

34
src/arch/sparc/isa.hh
View File

@@ -194,40 +194,6 @@ class ISA : public BaseISA
void setMiscRegNoEffect(int miscReg, RegVal val);
void setMiscReg(int miscReg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
{
switch (regId.classValue()) {
case IntRegClass:
return intRegClass[flattenIntIndex(regId.index())];
case FloatRegClass:
return floatRegClass[flattenFloatIndex(regId.index())];
case MiscRegClass:
return miscRegClass[flattenMiscIndex(regId.index())];
default:
break;
}
return regId;
}
int
flattenIntIndex(int reg) const
{
assert(reg < TotalInstIntRegs);
RegIndex flatIndex = intRegMap[reg];
assert(flatIndex < int_reg::NumRegs);
return flatIndex;
}
int flattenFloatIndex(int reg) const { return reg; }
int flattenVecIndex(int reg) const { return reg; }
int flattenVecElemIndex(int reg) const { return reg; }
int flattenVecPredIndex(int reg) const { return reg; }
// dummy
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
uint64_t
getExecutingAsid() const override
{

36
src/arch/x86/isa.hh
View File

@@ -78,42 +78,6 @@ class ISA : public BaseISA
void setMiscRegNoEffect(int miscReg, RegVal val);
void setMiscReg(int miscReg, RegVal val);
RegId
flattenRegId(const RegId& regId) const
{
switch (regId.classValue()) {
case IntRegClass:
return intRegClass[flattenIntIndex(regId.index())];
case FloatRegClass:
return floatRegClass[flattenFloatIndex(regId.index())];
case CCRegClass:
return ccRegClass[flattenCCIndex(regId.index())];
case MiscRegClass:
return miscRegClass[flattenMiscIndex(regId.index())];
default:
break;
}
return regId;
}
int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
int
flattenFloatIndex(int reg) const
{
if (reg >= float_reg::NumRegs) {
reg = float_reg::stack(reg - float_reg::NumRegs,
regVal[misc_reg::X87Top]);
}
return reg;
}
int flattenVecIndex(int reg) const { return reg; }
int flattenVecElemIndex(int reg) const { return reg; }
int flattenVecPredIndex(int reg) const { return reg; }
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
bool
inUserMode() const override
{