diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 4515555a8b..e7929b0132 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -198,97 +198,6 @@ namespace ArmISA void setMiscRegNoEffect(int misc_reg, RegVal val); void setMiscReg(int misc_reg, RegVal val); - RegId - flattenRegId(const RegId& regId) const - { - switch (regId.classValue()) { - case IntRegClass: - return intRegClass[flattenIntIndex(regId.index())]; - case FloatRegClass: - panic("ARM doesn't use FloatRegClass."); - case VecRegClass: - return vecRegClass[flattenVecIndex(regId.index())]; - case VecElemClass: - return vecElemClass[flattenVecElemIndex(regId.index())]; - case VecPredRegClass: - return vecPredRegClass[flattenVecPredIndex(regId.index())]; - case CCRegClass: - return ccRegClass[flattenCCIndex(regId.index())]; - case MiscRegClass: - return miscRegClass[flattenMiscIndex(regId.index())]; - case InvalidRegClass: - return RegId(); - } - panic("Unrecognized register class %d.", regId.classValue()); - } - - int - flattenIntIndex(int reg) const - { - assert(reg >= 0); - if (reg < int_reg::NumArchRegs) { - return intRegMap[reg]; - } else if (reg < int_reg::NumRegs) { - return reg; - } else if (reg == int_reg::Spx) { - CPSR cpsr = miscRegs[MISCREG_CPSR]; - ExceptionLevel el = opModeToEL( - (OperatingMode) (uint8_t) cpsr.mode); - if (!cpsr.sp && el != EL0) - return int_reg::Sp0; - switch (el) { - case EL3: - return int_reg::Sp3; - case EL2: - return int_reg::Sp2; - case EL1: - return int_reg::Sp1; - case EL0: - return int_reg::Sp0; - default: - panic("Invalid exception level"); - return 0; // Never happens. - } - } else { - return flattenIntRegModeIndex(reg); - } - } - - int - flattenFloatIndex(int reg) const - { - assert(reg >= 0); - return reg; - } - - int - flattenVecIndex(int reg) const - { - assert(reg >= 0); - return reg; - } - - int - flattenVecElemIndex(int reg) const - { - assert(reg >= 0); - return reg; - } - - int - flattenVecPredIndex(int reg) const - { - assert(reg >= 0); - return reg; - } - - int - flattenCCIndex(int reg) const - { - assert(reg >= 0); - return reg; - } - int flattenMiscIndex(int reg) const { diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index e744a86de4..73774fd221 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -142,17 +142,6 @@ namespace MipsISA public: ISA(const Params &p); - RegId flattenRegId(const RegId& regId) const { return regId; } - - int flattenIntIndex(int reg) const { return reg; } - int flattenFloatIndex(int reg) const { return reg; } - int flattenVecIndex(int reg) const { return reg; } - int flattenVecElemIndex(int reg) const { return reg; } - int flattenVecPredIndex(int reg) const { return reg; } - // dummy - int flattenCCIndex(int reg) const { return reg; } - int flattenMiscIndex(int reg) const { return reg; } - bool inUserMode() const override { diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 6c42f3271e..22641e8bb3 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -92,51 +92,6 @@ class ISA : public BaseISA fatal("Power does not currently have any misc regs defined\n"); } - RegId flattenRegId(const RegId& regId) const { return regId; } - - int - flattenIntIndex(int reg) const - { - return reg; - } - - int - flattenFloatIndex(int reg) const - { - return reg; - } - - int - flattenVecIndex(int reg) const - { - return reg; - } - - int - flattenVecElemIndex(int reg) const - { - return reg; - } - - int - flattenVecPredIndex(int reg) const - { - return reg; - } - - // dummy - int - flattenCCIndex(int reg) const - { - return reg; - } - - int - flattenMiscIndex(int reg) const - { - return reg; - } - bool inUserMode() const override { diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 81923b5aef..5ea7f14954 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -89,15 +89,6 @@ class ISA : public BaseISA void setMiscRegNoEffect(int misc_reg, RegVal val); void setMiscReg(int misc_reg, RegVal val); - RegId flattenRegId(const RegId ®Id) const { return regId; } - int flattenIntIndex(int reg) const { return reg; } - int flattenFloatIndex(int reg) const { return reg; } - int flattenVecIndex(int reg) const { return reg; } - int flattenVecElemIndex(int reg) const { return reg; } - int flattenVecPredIndex(int reg) const { return reg; } - int flattenCCIndex(int reg) const { return reg; } - int flattenMiscIndex(int reg) const { return reg; } - bool inUserMode() const override; void copyRegsFrom(ThreadContext *src) override; diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 67d6556568..56aa8c4e53 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -194,40 +194,6 @@ class ISA : public BaseISA void setMiscRegNoEffect(int miscReg, RegVal val); void setMiscReg(int miscReg, RegVal val); - RegId - flattenRegId(const RegId& regId) const - { - switch (regId.classValue()) { - case IntRegClass: - return intRegClass[flattenIntIndex(regId.index())]; - case FloatRegClass: - return floatRegClass[flattenFloatIndex(regId.index())]; - case MiscRegClass: - return miscRegClass[flattenMiscIndex(regId.index())]; - default: - break; - } - return regId; - } - - int - flattenIntIndex(int reg) const - { - assert(reg < TotalInstIntRegs); - RegIndex flatIndex = intRegMap[reg]; - assert(flatIndex < int_reg::NumRegs); - return flatIndex; - } - - int flattenFloatIndex(int reg) const { return reg; } - int flattenVecIndex(int reg) const { return reg; } - int flattenVecElemIndex(int reg) const { return reg; } - int flattenVecPredIndex(int reg) const { return reg; } - - // dummy - int flattenCCIndex(int reg) const { return reg; } - int flattenMiscIndex(int reg) const { return reg; } - uint64_t getExecutingAsid() const override { diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index e15a4be5cf..f5f77a391f 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -78,42 +78,6 @@ class ISA : public BaseISA void setMiscRegNoEffect(int miscReg, RegVal val); void setMiscReg(int miscReg, RegVal val); - RegId - flattenRegId(const RegId& regId) const - { - switch (regId.classValue()) { - case IntRegClass: - return intRegClass[flattenIntIndex(regId.index())]; - case FloatRegClass: - return floatRegClass[flattenFloatIndex(regId.index())]; - case CCRegClass: - return ccRegClass[flattenCCIndex(regId.index())]; - case MiscRegClass: - return miscRegClass[flattenMiscIndex(regId.index())]; - default: - break; - } - return regId; - } - - int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; } - - int - flattenFloatIndex(int reg) const - { - if (reg >= float_reg::NumRegs) { - reg = float_reg::stack(reg - float_reg::NumRegs, - regVal[misc_reg::X87Top]); - } - return reg; - } - - int flattenVecIndex(int reg) const { return reg; } - int flattenVecElemIndex(int reg) const { return reg; } - int flattenVecPredIndex(int reg) const { return reg; } - int flattenCCIndex(int reg) const { return reg; } - int flattenMiscIndex(int reg) const { return reg; } - bool inUserMode() const override {