fastmodel,cpu: Remove the flattenRegId ThreadContext method.

This is no longer used or necessary.

Change-Id: Ide8dd74b5d39b245d3d71979dd84c7fee60d566e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51234
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/fastmodel/iris/thread_context.hh

@@ -361,12 +361,6 @@ class ThreadContext : public gem5::ThreadContext
         setMiscRegNoEffect(misc_reg, val);
     }
 
-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     unsigned

src/cpu/checker/thread_context.hh

@@ -308,12 +308,6 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setMiscReg(misc_reg, val);
     }
 
-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        return actualTC->flattenRegId(regId);
-    }
-
     unsigned
     readStCondFailures() const override
     {

src/cpu/o3/thread_context.cc

@@ -196,12 +196,6 @@ ThreadContext::pcStateNoRecord(const PCStateBase &val)
     conditionalSquash();
 }
 
-RegId
-ThreadContext::flattenRegId(const RegId& regId) const
-{
-    return cpu->isa[thread->threadId()]->flattenRegId(regId);
-}
-
 void
 ThreadContext::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
 {

src/cpu/o3/thread_context.hh

@@ -210,8 +210,6 @@ class ThreadContext : public gem5::ThreadContext
      * write might have as defined by the architecture. */
     void setMiscReg(RegIndex misc_reg, RegVal val) override;
 
-    RegId flattenRegId(const RegId& regId) const override;
-
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
     unsigned

src/cpu/simple_thread.hh

@@ -290,12 +290,6 @@ class SimpleThread : public ThreadState, public ThreadContext
         return isa->setMiscReg(misc_reg, val);
     }
 
-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        return isa->flattenRegId(regId);
-    }
-
     unsigned readStCondFailures() const override { return storeCondFailures; }
 
     bool

src/cpu/thread_context.hh

@@ -219,8 +219,6 @@ class ThreadContext : public PCEventScope
 
     virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
 
-    virtual RegId flattenRegId(const RegId& reg_id) const = 0;
-
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() const = 0;