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arch-arm,cpu: Remove all uses of flattenRegId.

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RegIds can now be flattened directly.

Change-Id: I2a603c12bbc586720082363996f303cd3b43ac9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51233
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-01 04:54:26 -07:00
parent 8918021f63
commit ff4b675fb8
6 changed files with 40 additions and 44 deletions
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8
src/arch/arm/isa/insts/data64.isa
View File

@@ -312,8 +312,8 @@ let {{
msrMrs64EnabledCheckCode = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(%s, xc->tcBase());
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto flat_idx = (MiscRegIndex)isa->flattenMiscIndex(pre_flat);
// Check for read/write access right
if (fault = checkFaultAccessAArch64SysReg(flat_idx, Cpsr,
@@ -531,8 +531,8 @@ let {{
msrImmPermission = '''
auto pre_flat =
(MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto misc_index = (MiscRegIndex)isa->flattenMiscIndex(pre_flat);
if (fault = checkFaultAccessAArch64SysReg(misc_index,
Cpsr, xc->tcBase(), *this); fault != NoFault) {

3
src/arch/arm/isa/insts/fp.isa
View File

@@ -213,7 +213,8 @@ let {{
if (!isSecure(xc->tcBase()) && (cpsr.mode != MODE_HYP)) {
HCR hcr = Hcr;
bool hypTrap = false;
switch (xc->tcBase()->flattenRegId(miscRegClass[op1]).index()) {
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
switch (isa->flattenMiscIndex(op1)) {
case MISCREG_FPSID:
hypTrap = hcr.tid0;
break;

28
src/arch/arm/isa/insts/misc.isa
View File

@@ -889,8 +889,8 @@ let {{
exec_output += PredOpExecute.subst(bfiIop)
mrc14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
miscRegClass[op1]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(op1);
auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (!can_read || undefined) {
@@ -913,8 +913,8 @@ let {{
mcr14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
miscRegClass[dest]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(dest);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (undefined || !can_write) {
@@ -937,9 +937,8 @@ let {{
mrc15code = '''
int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(miscRegClass[
preFlatOp1]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatOp1);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -969,9 +968,8 @@ let {{
mcr15CheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(miscRegClass[
preFlatDest]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatDest);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -1015,9 +1013,8 @@ let {{
mrrc15code = '''
int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(miscRegClass[
preFlatOp1]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatOp1);
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -1047,9 +1044,8 @@ let {{
mcrr15code = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(miscRegClass[
preFlatDest]).index();
auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatDest);
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);

22
src/cpu/minor/scoreboard.cc
View File

@@ -89,13 +89,6 @@ Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index)
return ret;
}
/** Flatten a RegId, irrespective of what reg type it's pointing to */
static RegId
flattenRegIndex(const RegId& reg, ThreadContext *thread_context)
{
return thread_context->flattenRegId(reg);
}
void
Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
ThreadContext *thread_context, bool mark_unpredictable)
@@ -106,12 +99,13 @@ Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
StaticInstPtr staticInst = inst->staticInst;
unsigned int num_dests = staticInst->numDestRegs();
auto *isa = thread_context->getIsaPtr();
/** Mark each destination register */
for (unsigned int dest_index = 0; dest_index < num_dests;
dest_index++)
{
RegId reg = flattenRegIndex(
staticInst->destRegIdx(dest_index), thread_context);
RegId reg = staticInst->destRegIdx(dest_index).flatten(*isa);
Index index;
if (findIndex(reg, index)) {
@@ -151,9 +145,10 @@ Scoreboard::execSeqNumToWaitFor(MinorDynInstPtr inst,
StaticInstPtr staticInst = inst->staticInst;
unsigned int num_srcs = staticInst->numSrcRegs();
auto *isa = thread_context->getIsaPtr();
for (unsigned int src_index = 0; src_index < num_srcs; src_index++) {
RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
thread_context);
RegId reg = staticInst->srcRegIdx(src_index).flatten(*isa);
unsigned short int index;
if (findIndex(reg, index)) {
@@ -233,13 +228,14 @@ Scoreboard::canInstIssue(MinorDynInstPtr inst,
[num_relative_latencies-1];
}
auto *isa = thread_context->getIsaPtr();
/* For each source register, find the latest result */
unsigned int src_index = 0;
while (src_index < num_srcs && /* More registers */
ret /* Still possible */)
{
RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
thread_context);
RegId reg = staticInst->srcRegIdx(src_index).flatten(*isa);
unsigned short int index;
if (findIndex(reg, index)) {

13
src/cpu/o3/rename.cc
View File

@@ -1008,15 +1008,17 @@ Rename::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_src_regs = inst->numSrcRegs();
auto *isa = tc->getIsaPtr();
// Get the architectual register numbers from the source and
// operands, and redirect them to the right physical register.
for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
const RegId& src_reg = inst->srcRegIdx(src_idx);
const RegId flat_reg = src_reg.flatten(*isa);
PhysRegIdPtr renamed_reg;
renamed_reg = map->lookup(tc->flattenRegId(src_reg));
switch (src_reg.classValue()) {
renamed_reg = map->lookup(flat_reg);
switch (flat_reg.classValue()) {
case InvalidRegClass:
break;
case IntRegClass:
@@ -1037,13 +1039,13 @@ Rename::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
break;
default:
panic("Invalid register class: %d.", src_reg.classValue());
panic("Invalid register class: %d.", flat_reg.classValue());
}
DPRINTF(Rename,
"[tid:%i] "
"Looking up %s arch reg %i, got phys reg %i (%s)\n",
tid, src_reg.className(),
tid, flat_reg.className(),
src_reg.index(), renamed_reg->index(),
renamed_reg->className());
@@ -1076,13 +1078,14 @@ Rename::renameDestRegs(const DynInstPtr &inst, ThreadID tid)
gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_dest_regs = inst->numDestRegs();
auto *isa = tc->getIsaPtr();
// Rename the destination registers.
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
const RegId& dest_reg = inst->destRegIdx(dest_idx);
UnifiedRenameMap::RenameInfo rename_result;
RegId flat_dest_regid = tc->flattenRegId(dest_reg);
RegId flat_dest_regid = dest_reg.flatten(*isa);
flat_dest_regid.setNumPinnedWrites(dest_reg.getNumPinnedWrites());
rename_result = map->rename(flat_dest_regid);

10
src/cpu/simple_thread.hh
View File

@@ -319,7 +319,7 @@ class SimpleThread : public ThreadState, public ThreadContext
RegVal
getReg(const RegId &arch_reg) const override
{
const RegId reg = flattenRegId(arch_reg);
const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
@@ -335,7 +335,7 @@ class SimpleThread : public ThreadState, public ThreadContext
void
getReg(const RegId &arch_reg, void *val) const override
{
const RegId reg = flattenRegId(arch_reg);
const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
@@ -351,7 +351,7 @@ class SimpleThread : public ThreadState, public ThreadContext
void *
getWritableReg(const RegId &arch_reg) override
{
const RegId reg = flattenRegId(arch_reg);
const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
auto &reg_file = regFiles[reg.classValue()];
@@ -361,7 +361,7 @@ class SimpleThread : public ThreadState, public ThreadContext
void
setReg(const RegId &arch_reg, RegVal val) override
{
const RegId reg = flattenRegId(arch_reg);
const RegId reg = arch_reg.flatten(*isa);
if (reg.is(InvalidRegClass))
return;
@@ -379,7 +379,7 @@ class SimpleThread : public ThreadState, public ThreadContext
void
setReg(const RegId &arch_reg, const void *val) override
{
const RegId reg = flattenRegId(arch_reg);
const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();