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cpu: Eliminate the (get|set)RegFlat methods.

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These can now be performed with the (reg|set)Reg methods by using an
already flattened RegId.

Change-Id: Ie02cda224d96644061227eada100675d38797e57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51232
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-10-01 04:28:39 -07:00
parent c686c93d4d
commit 8918021f63
4 changed files with 0 additions and 149 deletions
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32
src/cpu/checker/thread_context.hh
View File

@@ -326,38 +326,6 @@ class CheckerThreadContext : public ThreadContext
actualTC->setStCondFailures(sc_failures);
}
RegVal
getRegFlat(const RegId &reg) const override
{
return actualTC->getRegFlat(reg);
}
void
getRegFlat(const RegId &reg, void *val) const override
{
actualTC->getRegFlat(reg, val);
}
void *
getWritableRegFlat(const RegId &reg) override
{
return actualTC->getWritableRegFlat(reg);
}
void
setRegFlat(const RegId &reg, RegVal val) override
{
actualTC->setRegFlat(reg, val);
checkerTC->setRegFlat(reg, val);
}
void
setRegFlat(const RegId &reg, const void *val) override
{
actualTC->setRegFlat(reg, val);
checkerTC->setRegFlat(reg, val);
}
// hardware transactional memory
void
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override

65
src/cpu/simple_thread.hh
View File

@@ -332,20 +332,6 @@ class SimpleThread : public ThreadState, public ThreadContext
return val;
}
RegVal
getRegFlat(const RegId &reg) const override
{
const RegIndex idx = reg.index();
const auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
RegVal val = reg_file.reg(idx);
DPRINTFV(reg_class.debug(), "Reading %s reg %d as %#x.\n",
reg.className(), idx, val);
return val;
}
void
getReg(const RegId &arch_reg, void *val) const override
{
@@ -362,19 +348,6 @@ class SimpleThread : public ThreadState, public ThreadContext
reg_class.valString(val));
}
void
getRegFlat(const RegId &reg, void *val) const override
{
const RegIndex idx = reg.index();
const auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
reg_file.get(idx, val);
DPRINTFV(reg_class.debug(), "Reading %s register %d as %s.\n",
reg.className(), idx, reg_class.valString(val));
}
void *
getWritableReg(const RegId &arch_reg) override
{
@@ -385,15 +358,6 @@ class SimpleThread : public ThreadState, public ThreadContext
return reg_file.ptr(idx);
}
void *
getWritableRegFlat(const RegId &reg) override
{
const RegIndex idx = reg.index();
auto &reg_file = regFiles[reg.classValue()];
return reg_file.ptr(idx);
}
void
setReg(const RegId &arch_reg, RegVal val) override
{
@@ -412,22 +376,6 @@ class SimpleThread : public ThreadState, public ThreadContext
reg_file.reg(idx) = val;
}
void
setRegFlat(const RegId &reg, RegVal val) override
{
if (reg.is(InvalidRegClass))
return;
const RegIndex idx = reg.index();
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
reg.className(), idx, val);
reg_file.reg(idx) = val;
}
void
setReg(const RegId &arch_reg, const void *val) override
{
@@ -444,19 +392,6 @@ class SimpleThread : public ThreadState, public ThreadContext
reg_file.set(idx, val);
}
void
setRegFlat(const RegId &reg, const void *val) override
{
const RegIndex idx = reg.index();
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %s.\n",
reg.className(), idx, reg_class.valString(val));
reg_file.set(idx, val);
}
// hardware transactional memory
void htmAbortTransaction(uint64_t htm_uid,
HtmFailureFaultCause cause) override;

32
src/cpu/thread_context.cc
View File

@@ -177,38 +177,6 @@ ThreadContext::setReg(const RegId &reg, RegVal val)
setReg(reg, &val);
}
RegVal
ThreadContext::getRegFlat(const RegId &reg) const
{
RegVal val;
getReg(reg, &val);
return val;
}
void
ThreadContext::getRegFlat(const RegId &reg, void *val) const
{
getReg(reg, val);
}
void *
ThreadContext::getWritableRegFlat(const RegId &reg)
{
return getWritableReg(reg);
}
void
ThreadContext::setRegFlat(const RegId &reg, RegVal val)
{
setReg(reg, &val);
}
void
ThreadContext::setRegFlat(const RegId &reg, const void *val)
{
setReg(reg, val);
}
void
serialize(const ThreadContext &tc, CheckpointOut &cp)
{

20
src/cpu/thread_context.hh
View File

@@ -235,26 +235,6 @@ class ThreadContext : public PCEventScope
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
/** @{ */
/**
* Flat register interfaces
*
* Some architectures have different registers visible in
* different modes. Such architectures "flatten" a register (see
* flattenRegId()) to map it into the
* gem5 register file. This interface provides a flat interface to
* the underlying register file, which allows for example
* serialization code to access all registers.
*/
virtual RegVal getRegFlat(const RegId &reg) const;
virtual void getRegFlat(const RegId &reg, void *val) const;
virtual void *getWritableRegFlat(const RegId &reg);
virtual void setRegFlat(const RegId &reg, RegVal val);
virtual void setRegFlat(const RegId &reg, const void *val);
/** @} */
// hardware transactional memory
virtual void htmAbortTransaction(uint64_t htm_uid,
HtmFailureFaultCause cause) = 0;