arch-sparc: Implement RegClass based register flattening.

Change-Id: Ib1d5b7ac7ff5aa6f35099fd9fd4530951c3efa19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51230
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/sparc/SConscript

@@ -38,6 +38,7 @@ Source('linux/syscalls.cc', tags='sparc isa')
 Source('nativetrace.cc', tags='sparc isa')
 Source('pagetable.cc', tags='sparc isa')
 Source('process.cc', tags='sparc isa')
+Source('regs/int.cc', tags='sparc isa')
 Source('remote_gdb.cc', tags='sparc isa')
 Source('se_workload.cc', tags='sparc isa')
 Source('tlb.cc', tags='sparc isa')

src/arch/sparc/isa.cc

@@ -79,7 +79,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 
 ISA::ISA(const Params &p) : BaseISA(p)
 {
-    _regClasses.push_back(&intRegClass);
+    _regClasses.push_back(&flatIntRegClass);
     _regClasses.push_back(&floatRegClass);
     _regClasses.push_back(&vecRegClass);
     _regClasses.push_back(&vecElemClass);

src/arch/sparc/isa.hh

@@ -168,6 +168,8 @@ class ISA : public BaseISA
     void reloadRegMap();
 
   public:
+    const RegIndex &mapIntRegId(RegIndex idx) const { return intRegMap[idx]; }
+
     void clear();
 
     PCStateBase *

src/arch/sparc/regs/int.cc

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/sparc/regs/int.hh"
+
+#include "arch/sparc/isa.hh"
+
+namespace gem5
+{
+
+namespace SparcISA
+{
+
+RegId
+IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
+{
+    auto &sparc_isa = static_cast<const SparcISA::ISA &>(isa);
+    return {flatIntRegClass, sparc_isa.mapIntRegId(id.index())};
+}
+
+} // namespace SparcISA
+} // namespace gem5

src/arch/sparc/regs/int.hh

@@ -68,8 +68,20 @@ const int NumRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroRegs;
 
 } // namespace int_reg
 
-inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
-        int_reg::NumRegs, debug::IntRegs);
+class IntRegClassOps : public RegClassOps
+{
+    RegId flatten(const BaseISA &isa, const RegId &id) const override;
+};
+
+inline constexpr IntRegClassOps intRegClassOps;
+
+inline constexpr RegClass intRegClass =
+    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs).
+    ops(intRegClassOps).
+    needsFlattening();
+
+inline constexpr RegClass flatIntRegClass =
+    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs);
 
 namespace int_reg
 {