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arch-mips,cpu-minor: Add MinorCPU to SPARC ISA

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While it may not be well supported, it's better to incorporate the
MinorCPU into the SPARC ISA gem5 binary than leave it out.

Change-Id: Iff8016b2a9857888cf66d1d2060581e979111b9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61538
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
2022-07-20 14:46:00 -07:00
committed by Bobby Bruce
parent c04551e494
commit ca59b200ad
1 changed files with 5 additions and 0 deletions
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5
src/arch/sparc/SparcCPU.py
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@@ -27,6 +27,7 @@ from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.BaseMinorCPU import BaseMinorCPU
from m5.objects.SparcDecoder import SparcDecoder
from m5.objects.SparcMMU import SparcMMU
from m5.objects.SparcInterrupts import SparcInterrupts
@@ -54,3 +55,7 @@ class SparcTimingSimpleCPU(BaseTimingSimpleCPU, SparcCPU):
class SparcO3CPU(BaseO3CPU, SparcCPU):
mmu = SparcMMU()
class SparcMinorCPU(BaseMinorCPU, SparcCPU):
mmu = SparcMMU()