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arch-vega: DS_OR_B32 does not return data

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The DS_OR_B32 instruction should not return data. This
changeset updates its implementation.

Change-Id: Ib5fccdbb69cd1ad2639bbf54824dc363a3fbf599
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62656
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Alexandru Dutu
2022-08-24 10:34:14 -07:00
committed by Alexandru Duțu
parent 56de5df7af
commit 241023329d
1 changed files with 1 additions and 13 deletions
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14
src/arch/amdgpu/vega/insts/instructions.cc
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@@ -34184,7 +34184,7 @@ namespace VegaISA
setFlag(MemoryRef);
setFlag(GroupSegment);
setFlag(AtomicOr);
setFlag(AtomicReturn);
setFlag(AtomicNoReturn);
} // Inst_DS__DS_OR_B32
Inst_DS__DS_OR_B32::~Inst_DS__DS_OR_B32()
@@ -34193,9 +34193,7 @@ namespace VegaISA
// --- description from .arch file ---
// 32b:
// tmp = MEM[ADDR];
// MEM[ADDR] |= DATA;
// RETURN_DATA = tmp.
void
Inst_DS__DS_OR_B32::execute(GPUDynInstPtr gpuDynInst)
{
@@ -34241,16 +34239,6 @@ namespace VegaISA
void
Inst_DS__DS_OR_B32::completeAcc(GPUDynInstPtr gpuDynInst)
{
VecOperandU32 vdst(gpuDynInst, extData.VDST);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
vdst[lane] = (reinterpret_cast<VecElemU32*>(
gpuDynInst->d_data))[lane];
}
}
vdst.write();
} // completeAcc
// --- Inst_DS__DS_XOR_B32 class methods ---