arch-arm: Properly assign the global tag to TLB entries

Translation entries from regimes with no ASID support are
tagged as global.

For complete translations we cannot simply check for the EL
being EL2 or EL3 as the EL2&0 translation regime does support
ASIDs to differentiate userspace host applications.

We therefore change the LongDescriptor::global method to cover
the EL2&0 case.

We also fix the partial translation logic which was labelling
partial translations as non global without checking for the
translation regime

Change-Id: I9375a34eba6ede97d70ed80e43ce363a57678d55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62452
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/mmu.cc

@@ -699,7 +699,7 @@ MMU::s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
 }
 
 bool
-MMU::hasUnprivRegime(ExceptionLevel el, CachedState &state)
+MMU::hasUnprivRegime(ExceptionLevel el, bool e2h)
 {
     switch (el) {
       case EL0:
@@ -708,13 +708,19 @@ MMU::hasUnprivRegime(ExceptionLevel el, CachedState &state)
         return true;
       case EL2:
         // EL2&0 or EL2
-        return state.hcr.e2h;
+        return e2h;
       case EL3:
       default:
         return false;
     }
 }
 
+bool
+MMU::hasUnprivRegime(ExceptionLevel el, CachedState &state)
+{
+    return hasUnprivRegime(el, state.hcr.e2h);
+}
+
 bool
 MMU::faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode,
               const bool is_priv, CachedState &state)

src/arch/arm/mmu.hh

@@ -390,6 +390,8 @@ class MMU : public BaseMMU
      */
     static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
 
+    static bool hasUnprivRegime(ExceptionLevel el, bool e2h);
+
   public:
     /** Lookup an entry in the TLB
      * @param vpn virtual address

src/arch/arm/table_walker.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2019, 2021 Arm Limited
+ * Copyright (c) 2010, 2012-2019, 2021-2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -2296,7 +2296,10 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor)
     te.valid          = true;
     te.longDescFormat = true;
     te.partial        = true;
-    te.global         = false;
+    // The entry is global if there is no address space identifier
+    // to differentiate translation contexts
+    te.global         = !mmu->hasUnprivRegime(
+        currState->el, currState->hcr.e2h);
     te.isHyp          = currState->isHyp;
     te.asid           = currState->asid;
     te.vmid           = currState->vmid;

src/arch/arm/table_walker.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2016, 2019, 2021 Arm Limited
+ * Copyright (c) 2010-2016, 2019, 2021-2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -647,9 +647,11 @@ class TableWalker : public ClockedObject
                                         !currState->secureLookup)) {
                 return false;  // ARM ARM issue C B3.6.3
             } else if (currState->aarch64) {
-                if (currState->el == EL2 || currState->el == EL3) {
-                    return true;  // By default translations are treated as global
-                                  // in AArch64 EL2 and EL3
+                if (!MMU::hasUnprivRegime(currState->el, currState->hcr.e2h)) {
+                    // By default translations are treated as global
+                    // in AArch64 for regimes without an unpriviledged
+                    // component
+                    return true;
                 } else if (currState->isSecure && !currState->secureLookup) {
                     return false;
                 }