cpu: Store the ISA class using BaseISA and not TheISA::ISA.

All generic functionality of the ISA class can now be accessed using
virtual methods, and so we don't need to keep the ISA specific version
of the class around any more.

Change-Id: I9f9a3de2dc68983276ef7efc008a18960412d509
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51238
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-02 00:10:33 -07:00
parent 5d00ba897f
commit ba4dba4cb3
4 changed files with 4 additions and 4 deletions

View File

@@ -216,7 +216,7 @@ CPU::CPU(const BaseO3CPUParams &params)
// Setup the rename map for whichever stages need it.
for (ThreadID tid = 0; tid < numThreads; tid++) {
isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
isa[tid] = params.isa[tid];
commitRenameMap[tid].init(regClasses, &regFile, &freeList);
renameMap[tid].init(regClasses, &regFile, &freeList);
}

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@@ -442,7 +442,7 @@ class CPU : public BaseCPU
/** Integer Register Scoreboard */
Scoreboard scoreboard;
std::vector<TheISA::ISA *> isa;
std::vector<BaseISA *> isa;
public:
/** Enum to give each stage a specific index, so when calling

View File

@@ -78,7 +78,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
{*_isa->regClasses().at(VecPredRegClass)},
{*_isa->regClasses().at(CCRegClass)}
}},
isa(dynamic_cast<TheISA::ISA *>(_isa)),
isa(_isa),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
system(_sys), mmu(_mmu), decoder(_decoder),

View File

@@ -99,7 +99,7 @@ class SimpleThread : public ThreadState, public ThreadContext
protected:
std::array<RegFile, CCRegClass + 1> regFiles;
TheISA::ISA *const isa; // one "instance" of the current ISA.
BaseISA *const isa; // one "instance" of the current ISA.
std::unique_ptr<PCStateBase> _pcState;