diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index a1805147a7..d436c9133c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -216,7 +216,7 @@ CPU::CPU(const BaseO3CPUParams &params)
 
     // Setup the rename map for whichever stages need it.
     for (ThreadID tid = 0; tid < numThreads; tid++) {
-        isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
+        isa[tid] = params.isa[tid];
         commitRenameMap[tid].init(regClasses, &regFile, &freeList);
         renameMap[tid].init(regClasses, &regFile, &freeList);
     }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index db3474da58..a520e01023 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -442,7 +442,7 @@ class CPU : public BaseCPU
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;
 
-    std::vector<TheISA::ISA *> isa;
+    std::vector<BaseISA *> isa;
 
   public:
     /** Enum to give each stage a specific index, so when calling
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 0ca40c5dc8..42bad0c19d 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -78,7 +78,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
           {*_isa->regClasses().at(VecPredRegClass)},
           {*_isa->regClasses().at(CCRegClass)}
       }},
-      isa(dynamic_cast<TheISA::ISA *>(_isa)),
+      isa(_isa),
       predicate(true), memAccPredicate(true),
       comInstEventQueue("instruction-based event queue"),
       system(_sys), mmu(_mmu), decoder(_decoder),
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 879b653d23..a19661044d 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -99,7 +99,7 @@ class SimpleThread : public ThreadState, public ThreadContext
   protected:
     std::array<RegFile, CCRegClass + 1> regFiles;
 
-    TheISA::ISA *const isa;    // one "instance" of the current ISA.
+    BaseISA *const isa;    // one "instance" of the current ISA.
 
     std::unique_ptr<PCStateBase> _pcState;