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arch-x86: Fix gem5Op not writing to rax in time

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This commit adds rax to the destination register of gem5Op and sets the
result correctly. So that in O3CPU, the correct register dependency is
determined and the following instructions can get the correct value.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1273

Change-Id: Ic6e094a548648da09ee08e8d5f7d9afa5408b18e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62992
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Jiajie Chen
2022-09-02 01:52:16 +08:00
parent 241023329d
commit 63556899e4
1 changed files with 3 additions and 1 deletions
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4
src/arch/x86/isa/decoder/two_byte_opcodes.isa
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@@ -157,8 +157,10 @@
// instructions.
//0x04: loadall_or_reset_or_hang();
0x4: BasicOperate::gem5Op({{
uint64_t result;
bool recognized = pseudo_inst::pseudoInst<X86PseudoInstABI>(
xc->tcBase(), IMMEDIATE);
xc->tcBase(), IMMEDIATE, result);
Rax = result;
if (!recognized)
fault = std::make_shared<InvalidOpcode>();
}}, IsNonSpeculative);