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misc: Stop excluding code when building the NULL ISA.

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The BaseCPU needs a little extra hacking because it tries to create
default objects based on what the ISA is. If the ISA isn't recognized,
then the types will be set to None, and some extra checks have been
added as the type is set up.

Change-Id: Ia3cae313e1a96a953d2316d9192f41a8fd28c141
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62195
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-25 05:44:13 -07:00
parent aefc0576a2
commit a13e3debed
19 changed files with 16 additions and 81 deletions
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3
src/Doxyfile
View File

@@ -1284,8 +1284,7 @@ INCLUDE_FILE_PATTERNS =
# or name=definition (no spaces). If the definition and the = are
# omitted =1 is assumed.
PREDEFINED = DOXYGEN_SHOULD_SKIP_THIS \
IS_NULL_ISA
PREDEFINED = DOXYGEN_SHOULD_SKIP_THIS
# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
# this tag can be used to specify a list of macro names that should be expanded.

1
src/SConscript
View File

@@ -576,7 +576,6 @@ def makeTheISA(source, target, env):
#ifndef __CONFIG_THE_ISA_HH__
#define __CONFIG_THE_ISA_HH__
#define IS_NULL_ISA ${{is_null_isa}}
#define TheISA ${{namespace(target_isa)}}
#endif // __CONFIG_THE_ISA_HH__''')

3
src/base/SConscript
View File

@@ -66,8 +66,7 @@ Source('pixel.cc')
GTest('pixel.test', 'pixel.test.cc', 'pixel.cc')
Source('pollevent.cc')
Source('random.cc')
if env['CONF']['TARGET_ISA'] != 'null':
Source('remote_gdb.cc')
Source('remote_gdb.cc')
Source('socket.cc')
GTest('socket.test', 'socket.test.cc', 'socket.cc')
Source('statistics.cc')

3
src/cpu/SConscript
View File

@@ -86,9 +86,6 @@ Source('pc_event.cc')
SimObject('FuncUnit.py', sim_objects=['OpDesc', 'FUDesc'], enums=['OpClass'])
SimObject('StaticInstFlags.py', enums=['StaticInstFlags'])
if env['CONF']['TARGET_ISA'] == 'null':
Return()
# Only build the protobuf instructions tracer if we have protobuf support.
SimObject('InstPBTrace.py', sim_objects=['InstPBTrace'], tags='protobuf')
Source('inst_pb_trace.cc', tags='protobuf')

6
src/cpu/base.hh
View File

@@ -47,10 +47,6 @@
// Before we do anything else, check if this build is the NULL ISA,
// and if so stop here
#include "config/the_isa.hh"
#if IS_NULL_ISA
#error Including BaseCPU in a system without CPU support
#else
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
#include "debug/Mwait.hh"
@@ -650,6 +646,4 @@ class BaseCPU : public ClockedObject
} // namespace gem5
#endif // !IS_NULL_ISA
#endif // __CPU_BASE_HH__

3
src/cpu/pred/SConscript
View File

@@ -28,9 +28,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('BranchPredictor.py', sim_objects=[
'IndirectPredictor', 'SimpleIndirectPredictor', 'BranchPredictor',
'LocalBP', 'TournamentBP', 'BiModeBP', 'TAGEBase', 'TAGE', 'LoopPredictor',

3
src/cpu/trace/SConscript
View File

@@ -1,8 +1,5 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
# Only build TraceCPU if we have support for protobuf as TraceCPU relies on it
SimObject('TraceCPU.py', sim_objects=['TraceCPU'], tags='protobuf')
Source('trace_cpu.cc', tags='protobuf')

3
src/dev/SConscript
View File

@@ -47,9 +47,6 @@ DebugFlag('DMA')
SimObject('Platform.py', sim_objects=['Platform'])
Source('platform.cc')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('BadDevice.py', sim_objects=['BadDevice'])
Source('baddev.cc')

3
src/dev/i2c/SConscript
View File

@@ -37,8 +37,5 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('I2C.py', sim_objects=['I2CDevice', 'I2CBus'])
Source('bus.cc')

4
src/dev/net/dist_iface.cc
View File

@@ -868,12 +868,10 @@ DistIface::toggleSync(ThreadContext *tc)
// stop point. Suspend execution of all local thread contexts.
// Dist-gem5 will reactivate all thread contexts when everyone has
// reached the sync stop point.
#if !IS_NULL_ISA
for (auto *tc: primary->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesce();
}
#endif
} else {
inform("Request toggling syncronization on\n");
primary->syncEvent->start();
@@ -882,12 +880,10 @@ DistIface::toggleSync(ThreadContext *tc)
// nodes to prevent causality errors. We can also schedule CPU
// activation here, since we know exactly when the next sync will
// occur.
#if !IS_NULL_ISA
for (auto *tc: primary->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesceTick(primary->syncEvent->when() + 1);
}
#endif
}
}

3
src/dev/ps2/SConscript
View File

@@ -37,9 +37,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('PS2.py', sim_objects=[
'PS2Device', 'PS2Keyboard', 'PS2Mouse', 'PS2TouchKit'])
Source('device.cc')

3
src/dev/serial/SConscript
View File

@@ -40,9 +40,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('Serial.py', sim_objects=['SerialDevice', 'SerialNullDevice'])
SimObject('Terminal.py', sim_objects=['Terminal'], enums=['TerminalDump'])
SimObject('Uart.py', sim_objects=['Uart', 'SimpleUart', 'Uart8250'])

3
src/dev/storage/SConscript
View File

@@ -40,9 +40,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
# Controllers
SimObject('Ide.py', sim_objects=['IdeDisk', 'IdeController'], enums=['IdeID'])

3
src/dev/virtio/SConscript
View File

@@ -37,9 +37,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('VirtIO.py', sim_objects=[
'VirtIODeviceBase', 'VirtIODummyDevice', 'PciVirtIO'])
SimObject('VirtIOConsole.py', sim_objects=['VirtIOConsole'])

3
src/kern/SConscript
View File

@@ -28,9 +28,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
Source('linux/events.cc')
Source('linux/linux.cc')
Source('linux/helpers.cc')

7
src/mem/SConscript
View File

@@ -104,10 +104,9 @@ Source('port_terminator.cc')
GTest('translation_gen.test', 'translation_gen.test.cc')
if env['CONF']['TARGET_ISA'] != 'null':
Source('translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
Source('translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
if env['HAVE_DRAMSIM']:
SimObject('DRAMSim2.py', sim_objects=['DRAMSim2'])

23
src/sim/SConscript
View File

@@ -104,18 +104,17 @@ GTest('proxy_ptr.test', 'proxy_ptr.test.cc')
GTest('serialize.test', 'serialize.test.cc', with_tag('gem5 serialize'))
GTest('serialize_handlers.test', 'serialize_handlers.test.cc')
if env['CONF']['TARGET_ISA'] != 'null':
SimObject('InstTracer.py', sim_objects=['InstTracer'])
SimObject('Process.py', sim_objects=['Process', 'EmulatedDriver'])
Source('faults.cc')
Source('process.cc')
Source('fd_array.cc')
Source('fd_entry.cc')
Source('mem_state.cc')
Source('pseudo_inst.cc')
Source('syscall_emul.cc')
Source('syscall_desc.cc')
Source('vma.cc')
SimObject('InstTracer.py', sim_objects=['InstTracer'])
SimObject('Process.py', sim_objects=['Process', 'EmulatedDriver'])
Source('faults.cc')
Source('process.cc')
Source('fd_array.cc')
Source('fd_entry.cc')
Source('mem_state.cc')
Source('pseudo_inst.cc')
Source('syscall_emul.cc')
Source('syscall_desc.cc')
Source('vma.cc')
DebugFlag('Checkpoint')
DebugFlag('Config')

12
src/sim/system.cc
View File

@@ -50,9 +50,7 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#if !IS_NULL_ISA
#include "cpu/base.hh"
#endif
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/Quiesce.hh"
@@ -73,10 +71,8 @@ std::vector<System *> System::systemList;
void
System::Threads::Thread::resume()
{
# if !IS_NULL_ISA
DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
context->activate();
# endif
}
std::string
@@ -114,13 +110,11 @@ System::Threads::replace(ThreadContext *tc, ContextID id)
{
auto &t = thread(id);
panic_if(!t.context, "Can't replace a context which doesn't exist.");
# if !IS_NULL_ISA
if (t.resumeEvent->scheduled()) {
Tick when = t.resumeEvent->when();
t.context->getCpuPtr()->deschedule(t.resumeEvent);
tc->getCpuPtr()->schedule(t.resumeEvent, when);
}
# endif
t.context = tc;
}
@@ -152,17 +146,14 @@ void
System::Threads::quiesce(ContextID id)
{
auto &t = thread(id);
# if !IS_NULL_ISA
[[maybe_unused]] BaseCPU *cpu = t.context->getCpuPtr();
DPRINTFS(Quiesce, cpu, "quiesce()\n");
# endif
t.quiesce();
}
void
System::Threads::quiesceTick(ContextID id, Tick when)
{
# if !IS_NULL_ISA
auto &t = thread(id);
BaseCPU *cpu = t.context->getCpuPtr();
@@ -170,7 +161,6 @@ System::Threads::quiesceTick(ContextID id, Tick when)
t.quiesce();
cpu->reschedule(t.resumeEvent, when, true);
# endif
}
int System::numSystemsRunning = 0;
@@ -361,9 +351,7 @@ System::unserialize(CheckpointIn &cp)
!when || !t.resumeEvent) {
continue;
}
# if !IS_NULL_ISA
t.context->getCpuPtr()->schedule(t.resumeEvent, when);
# endif
}
// also unserialize the memories in the system

8
src/sim/workload.cc
View File

@@ -44,10 +44,8 @@ Workload::registerThreadContext(ThreadContext *tc)
panic_if(!success, "Failed to add thread context %d.",
tc->contextId());
# if !IS_NULL_ISA
if (gdb)
gdb->addThreadContext(tc);
# endif
}
void
@@ -66,10 +64,8 @@ Workload::replaceThreadContext(ThreadContext *tc)
panic_if(!success,
"Failed to insert replacement thread context %d.", id);
# if !IS_NULL_ISA
if (gdb)
gdb->replaceThreadContext(tc);
# endif
return;
}
@@ -79,12 +75,10 @@ Workload::replaceThreadContext(ThreadContext *tc)
bool
Workload::trapToGdb(int signal, ContextID ctx_id)
{
# if !IS_NULL_ISA
if (gdb && gdb->isAttached()) {
gdb->trap(ctx_id, signal);
return true;
}
# endif
return false;
};
@@ -93,7 +87,6 @@ Workload::startup()
{
SimObject::startup();
# if !IS_NULL_ISA
// Now that we're about to start simulation, wait for GDB connections if
// requested.
if (gdb && waitForRemoteGDB) {
@@ -101,7 +94,6 @@ Workload::startup()
gdb->port());
gdb->connect();
}
# endif
}
} // namespace gem5