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stdlib,tests: Add BaseCPUProcessor to stdlib

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The BaseCPUProcessor is processor containing BaseCPUCores. This gives
gem5 stdlib users a way to create processors containing BaseCPU
SimObjects. While SimpleProcessor does this by-proxy (the user simply
specifies the desires CPUType and ISA and the correct BaseCPU
instantiation is chosen), this new Processor allows a more raw passing
of BaseCPU objects.

The SimpleProcessor now inherrits from this BaseCPUProcessor to avoid
duplcation of functionality. A refactor to achieve this was moving the
setting of the board's memory mode from the SimpleProcessor's
"incorporate_processor" function to the BaseCPUProcessor's then altering
it to determine MemMode based on BaseCPU subclass rather than the
CPUType.

The tests/gem5/configs/simple_binary_run.py test script has been
extended to create an stdlib run with a BaseCPUProcessor instead of the
SimpleProcessor and tests have been included to ensure the
BaseCPUProcessor functions as intended.

Multiple cores comprising of different BaseCPU types has not been tested
and is not officially supported as of this commit.

Change-Id: I229943ab98ece39646f1b4feb909250bb5c61772
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62353
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Bobby R. Bruce
2022-08-12 14:19:34 -07:00
committed by Bobby Bruce
parent 5e281c969b
commit 3238822e9e
5 changed files with 215 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/python/SConscript
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@@ -204,6 +204,8 @@ PySource('gem5.components.processors',
'gem5/components/processors/base_cpu_core.py')
PySource('gem5.components.processors',
'gem5/components/processors/simple_processor.py')
PySource('gem5.components.processors',
'gem5/components/processors/base_cpu_processor.py')
PySource('gem5.components.processors',
'gem5/components/processors/simple_switchable_processor.py')
PySource('gem5.components.processors',

103
src/python/gem5/components/processors/base_cpu_processor.py Normal file
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@@ -0,0 +1,103 @@
# Copyright (c) 2022 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from .base_cpu_core import BaseCPUCore
from ..boards.mem_mode import MemMode
from ...utils.override import overrides
from ..boards.mem_mode import MemMode
from .abstract_processor import AbstractProcessor
from ..boards.abstract_board import AbstractBoard
from typing import List
from m5.util import warn
from m5.objects import (
BaseO3CPU,
BaseMinorCPU,
BaseAtomicSimpleCPU,
BaseNonCachingSimpleCPU,
BaseTimingSimpleCPU,
)
class BaseCPUProcessor(AbstractProcessor):
"""
A processor constructed from a List of BaseCPUCores.
This gives gem5 stdlib users a way to create processors containing BaseCPU
SimObjects. While SimpleProcessor does this by-proxy (the user simply
specifies the desires CPUType and ISA and the correct BaseCPU
instantiation is chosen), this Processor allows a more raw passing
of BaseCPU objects.
Disclaimer
----------
Multiple cores comprising of different BaseCPU types has not been tested
and is not officially supported.
"""
def __init__(self, cores: List[BaseCPUCore]):
super().__init__(cores=cores)
if any(core.is_kvm_core() for core in self.get_cores()):
from m5.objects import KvmVM
self.kvm_vm = KvmVM()
@overrides(AbstractProcessor)
def incorporate_processor(self, board: AbstractBoard) -> None:
if any(core.is_kvm_core() for core in self.get_cores()):
board.kvm_vm = self.kvm_vm
# To get the KVM CPUs to run on different host CPUs
# Specify a different event queue for each CPU
for i, core in enumerate(self.cores):
for obj in core.get_simobject().descendants():
obj.eventq_index = 0
core.get_simobject().eventq_index = i + 1
board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
elif isinstance(
self.cores[0].get_simobject(),
(BaseTimingSimpleCPU, BaseO3CPU, BaseMinorCPU),
):
board.set_mem_mode(MemMode.TIMING)
elif isinstance(
self.cores[0].get_simobject(), BaseNonCachingSimpleCPU
):
board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
elif isinstance(self.cores[0].get_simobject(), BaseAtomicSimpleCPU):
if board.get_cache_hierarchy().is_ruby():
warn(
"Using an atomic core with Ruby will result in "
"'atomic_noncaching' memory mode. This will skip caching "
"completely."
)
else:
board.set_mem_mode(MemMode.ATOMIC)
else:
raise NotImplementedError

60
src/python/gem5/components/processors/simple_processor.py
View File

@@ -25,21 +25,16 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from ...utils.override import overrides
from ..boards.mem_mode import MemMode
from .base_cpu_processor import BaseCPUProcessor
from ..processors.simple_core import SimpleCore
from m5.util import warn
from .abstract_processor import AbstractProcessor
from .cpu_types import CPUTypes
from ...isas import ISA
from ..boards.abstract_board import AbstractBoard
from typing import Optional
class SimpleProcessor(AbstractProcessor):
class SimpleProcessor(BaseCPUProcessor):
"""
A SimpleProcessor contains a number of cores of SimpleCore objects of the
same CPUType.
@@ -59,51 +54,8 @@ class SimpleProcessor(AbstractProcessor):
construction.
"""
super().__init__(
cores=self._create_cores(
cpu_type=cpu_type, num_cores=num_cores, isa=isa
)
cores=[
SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)
for i in range(num_cores)
]
)
self._cpu_type = cpu_type
if self._cpu_type == CPUTypes.KVM:
from m5.objects import KvmVM
self.kvm_vm = KvmVM()
def _create_cores(
self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA]
):
return [
SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)
for i in range(num_cores)
]
@overrides(AbstractProcessor)
def incorporate_processor(self, board: AbstractBoard) -> None:
if self._cpu_type == CPUTypes.KVM:
board.kvm_vm = self.kvm_vm
# Set the memory mode.
if self._cpu_type in (CPUTypes.TIMING, CPUTypes.O3, CPUTypes.MINOR):
board.set_mem_mode(MemMode.TIMING)
elif self._cpu_type == CPUTypes.KVM:
board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
elif self._cpu_type == CPUTypes.ATOMIC:
if board.get_cache_hierarchy().is_ruby():
warn(
"Using an atomic core with Ruby will result in "
"'atomic_noncaching' memory mode. This will skip caching "
"completely."
)
else:
board.set_mem_mode(MemMode.ATOMIC)
else:
raise NotImplementedError
if self._cpu_type == CPUTypes.KVM:
# To get the KVM CPUs to run on different host CPUs
# Specify a different event queue for each CPU
for i, core in enumerate(self.cores):
for obj in core.get_simobject().descendants():
obj.eventq_index = 0
core.get_simobject().eventq_index = i + 1

40
tests/gem5/configs/simple_binary_run.py
View File

@@ -39,11 +39,17 @@ from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set
import argparse
from python.gem5.components.processors.base_cpu_core import BaseCPUCore
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
)
@@ -60,6 +66,13 @@ parser.add_argument(
"isa", type=str, choices=get_isas_str_set(), help="The ISA used"
)
parser.add_argument(
"-b",
"--base-cpu-processor",
action="store_true",
help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
)
parser.add_argument(
"-r",
"--resource-directory",
@@ -82,11 +95,28 @@ args = parser.parse_args()
# Setup the system.
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
processor = SimpleProcessor(
cpu_type=get_cpu_type_from_str(args.cpu),
isa=get_isa_from_str(args.isa),
num_cores=1,
)
if args.base_cpu_processor:
cores = [
BaseCPUCore(
core=SimpleCore.cpu_simobject_factory(
cpu_type=get_cpu_type_from_str(args.cpu),
isa=get_isa_from_str(args.isa),
core_id=0,
),
isa=get_isa_from_str(args.isa),
)
]
processor = BaseCPUProcessor(
cores=cores,
)
else:
processor = SimpleProcessor(
cpu_type=get_cpu_type_from_str(args.cpu),
isa=get_isa_from_str(args.isa),
num_cores=1,
)
motherboard = SimpleBoard(
clk_freq="3GHz",

69
tests/gem5/stdlib/test_base_cpu_processor.py Normal file
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@@ -0,0 +1,69 @@
# Copyright (c) 2022 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from testlib import *
"""
These tests are designed to test the BaseCPUProcessor. It utilizes the
tests/gem5/configs/simple_binary_run.py to run a simple SE-mode simualation
with different configurations of the BaseCPUProcessor.
"""
gem5_verify_config(
name=f"BaseCPUProcessor-x86-hello",
verifiers=(),
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["x86-hello64-static", "timing", "x86", "-b"],
valid_isas=(constants.vega_x86_tag,),
length=constants.quick_tag,
)
gem5_verify_config(
name=f"BaseCPUProcessor-riscv-hello",
verifiers=(),
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["riscv-hello", "atomic", "riscv", "-b"],
valid_isas=(constants.riscv_tag,),
length=constants.quick_tag,
)
gem5_verify_config(
name=f"BaseCPUProcessor-arm-hello",
verifiers=(),
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["arm-hello64-static", "o3", "arm", "-b"],
valid_isas=(constants.arm_tag,),
length=constants.quick_tag,
)