arch: Bump MaxVecRegLenInBytes to 2^16

Per chapter 2 of RVV 1.0 specs [1], RISCV vector extension supports
vector register size of upto 64kB.

[1] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

Change-Id: Ib62eb9d59006403f6fe08cfb06cb8a1bc0adbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/arch/generic/vec_reg.hh

@@ -110,7 +110,7 @@
 namespace gem5
 {
 
-constexpr unsigned MaxVecRegLenInBytes = 4096;
+constexpr unsigned MaxVecRegLenInBytes = 1ULL << 16; // 2^16 bytes
 
 /**
  * Vector Register Abstraction