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misc: Run pre-commit run on all files in repo

Browse Source 
The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Bobby R. Bruce
2022-08-22 12:34:19 -07:00
committed by Bobby Bruce
parent 64add0e04d
commit 2bc5a8b71a
181 changed files with 1445 additions and 1229 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/fastmodel/GIC/FastModelGIC.py
View File

@@ -865,7 +865,7 @@ class FastModelGIC(BaseGic):
return [int(r.split("=")[1], 16) for r in redists]
def get_addr_ranges(self):
""" Return address ranges that should be served by this GIC """
"""Return address ranges that should be served by this GIC"""
sc_gic = self.sc_gic
gic_frame_size = 0x10000
# Add range of distributor

6
src/arch/arm/fastmodel/arm_fast_model.py
View File

@@ -31,9 +31,9 @@ import _m5.arm_fast_model
def set_armlmd_license_file(force=False):
"""Set the ARMLMD_LICENSE_FILE environment variable. If "force" is
False, then it will only be set if it wasn't already set in the
environment. The value it's set to is the one gem5 was built with.
"""
False, then it will only be set if it wasn't already set in the
environment. The value it's set to is the one gem5 was built with.
"""
key = "ARMLMD_LICENSE_FILE"
license_file = buildEnv[key]
if force or key not in os.environ:

1
src/arch/arm/isa/copyright.txt
View File

@@ -35,4 +35,3 @@
// ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
// IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGES.

1
src/arch/arm/isa/decoder/aarch64.isa
View File

@@ -43,4 +43,3 @@
Aarch64::aarch64();

1
src/arch/arm/isa/decoder/arm.isa
View File

@@ -132,4 +132,3 @@ format DataOp {
}
}
}

1
src/arch/arm/isa/formats/breakpoint.isa
View File

@@ -56,4 +56,3 @@ def format ArmBkptHlt() {{
}
'''
}};

1
src/arch/arm/isa/formats/mem.isa
View File

@@ -1154,4 +1154,3 @@ def format Thumb16MemLit() {{
}
''' % loadImmClassName(False, True, False)
}};

1
src/arch/arm/isa/formats/pred.isa
View File

@@ -202,4 +202,3 @@ def format PredImmOp(code, *opt_flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = PredOpExecute.subst(iop)
}};

1
src/arch/arm/isa/insts/crypto64.isa
View File

@@ -167,4 +167,3 @@ let {{
cryptoRegRegRegInst("sha256su1", "SHA256SU164", "SimdShaSigma3Op",
sha2_enabled, sha256_su1Code)
}};

1
src/arch/arm/isa/insts/mem.isa
View File

@@ -229,4 +229,3 @@ let {{
raise Exception("Illegal combination of post and writeback")
return base
}};

2
src/arch/arm/isa/templates/branch.isa
View File

@@ -186,5 +186,3 @@ def template BranchTarget {{
return std::unique_ptr<PCStateBase>{pc_ptr};
}
}};

1
src/arch/arm/isa/templates/mem.isa
View File

@@ -1288,4 +1288,3 @@ def template LoadImmConstructor {{
#endif
}
}};

45
src/arch/isa_parser/isa_parser.py
View File

@@ -112,12 +112,11 @@ class Template(object):
operands = SubOperandList(self.parser, compositeCode, d.operands)
myDict["reg_idx_arr_decl"] = (
"RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]"
% (
d.operands.numSrcRegs + d.srcRegIdxPadding,
d.operands.numDestRegs + d.destRegIdxPadding,
)
myDict[
"reg_idx_arr_decl"
] = "RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]" % (
d.operands.numSrcRegs + d.srcRegIdxPadding,
d.operands.numDestRegs + d.destRegIdxPadding,
)
# The reinterpret casts are largely because an array with a known
@@ -960,15 +959,15 @@ class ISAParser(Grammar):
# They are all processed as they are seen.
def p_def_or_output(self, t):
"""def_or_output : name_decl
| def_format
| def_bitfield
| def_bitfield_struct
| def_template
| def_operand_types
| def_operands
| output
| global_let
| split"""
| def_format
| def_bitfield
| def_bitfield_struct
| def_template
| def_operand_types
| def_operands
| output
| global_let
| split"""
# Utility function used by both invocations of splitting - explicit
# 'split' keyword and split() function inside "let {{ }};" blocks.
@@ -992,8 +991,8 @@ class ISAParser(Grammar):
def p_output_type(self, t):
"""output_type : DECODER
| HEADER
| EXEC"""
| HEADER
| EXEC"""
t[0] = t[1]
# ISA name declaration looks like "namespace <foo>;"
@@ -1175,7 +1174,7 @@ del wrap
def p_param_list_1(self, t):
"""param_list : positional_param_list
| nonpositional_param_list"""
| nonpositional_param_list"""
t[0] = t[1]
def p_positional_param_list_0(self, t):
@@ -1196,7 +1195,7 @@ del wrap
def p_nonpositional_param_list_1(self, t):
"""nonpositional_param_list : keyword_param_list
| excess_args_param"""
| excess_args_param"""
t[0] = t[1]
def p_keyword_param_list_0(self, t):
@@ -1360,7 +1359,7 @@ StaticInstPtr
t[0] = ["default:"]
def prep_int_lit_case_label(self, lit):
if lit >= 2 ** 32:
if lit >= 2**32:
return "case %#xULL: " % lit
else:
return "case %#x: " % lit
@@ -1468,9 +1467,9 @@ StaticInstPtr
#
def p_expr_0(self, t):
"""expr : ID
| INTLIT
| STRLIT
| CODELIT"""
| INTLIT
| STRLIT
| CODELIT"""
t[0] = t[1]
def p_expr_1(self, t):

10
src/arch/micro_asm.py
View File

@@ -375,7 +375,7 @@ def p_file(t):
def p_opt_rom_or_macros_0(t):
"opt_rom_or_macros : "
"opt_rom_or_macros :"
def p_opt_rom_or_macros_1(t):
@@ -392,7 +392,7 @@ def p_rom_or_macros_1(t):
def p_rom_or_macro_0(t):
"""rom_or_macro : rom_block
| macroop_def"""
| macroop_def"""
# Defines a section of microcode that should go in the current ROM
@@ -466,20 +466,20 @@ def p_statement(t):
# A statement can be a microop or an assembler directive
def p_content_of_statement_0(t):
"""content_of_statement : microop
| directive"""
| directive"""
t[0] = t[1]
# Ignore empty statements
def p_content_of_statement_1(t):
"content_of_statement : "
"content_of_statement :"
pass
# Statements are ended by newlines or a semi colon
def p_end_of_statement(t):
"""end_of_statement : NEWLINE
| SEMI"""
| SEMI"""
pass

1
src/arch/mips/isa/base.isa
View File

@@ -145,4 +145,3 @@ output decoder {{
}
}};

2
src/arch/mips/isa/decoder.isa
View File

@@ -2545,5 +2545,3 @@ decode OPCODE_HI default Unknown::unknown() {
0x6: CP2Unimpl::sdc2();
}
}

4
src/arch/mips/isa/formats/branch.isa
View File

@@ -326,7 +326,3 @@ def format Jump(code, *opt_flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

2
src/arch/mips/isa/formats/control.isa
View File

@@ -241,5 +241,3 @@ def format CP1Control(code, *flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = CP1Execute.subst(iop)
}};

3
src/arch/mips/isa/formats/dsp.isa
View File

@@ -208,6 +208,3 @@ def format DspHiLoOp(code, *opt_flags) {{
exec_output = DspHiLoExecute.subst(iop)
}};

1
src/arch/mips/isa/formats/fp.isa
View File

@@ -363,4 +363,3 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

1
src/arch/mips/isa/formats/noop.isa
View File

@@ -134,4 +134,3 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
def format Nop() {{
decode_block = 'return new Nop(\"\",machInst);\n'
}};

1
src/arch/mips/isa/formats/unimp.isa
View File

@@ -273,4 +273,3 @@ def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

1
src/arch/mips/isa/formats/unknown.isa
View File

@@ -77,4 +77,3 @@ output exec {{
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

1
src/arch/power/isa/formats/unimp.isa
View File

@@ -141,4 +141,3 @@ def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

1
src/arch/power/isa/formats/unknown.isa
View File

@@ -82,4 +82,3 @@ output exec {{
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

2
src/arch/power/isa/formats/util.isa
View File

@@ -224,5 +224,3 @@ output decoder {{
}
}};

2
src/arch/riscv/gdb-xml/riscv-64bit-cpu.xml
View File

@@ -45,4 +45,4 @@
<reg name="t5" bitsize="64" type="int"/>
<reg name="t6" bitsize="64" type="int"/>
<reg name="pc" bitsize="64" type="code_ptr"/>
</feature>
</feature>

2
src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
View File

@@ -245,4 +245,4 @@
<reg name="mucounteren" bitsize="64"/>
<reg name="mscounteren" bitsize="64"/>
<reg name="mhcounteren" bitsize="64"/> -->
</feature>
</feature>

2
src/arch/riscv/gdb-xml/riscv-64bit-fpu.xml
View File

@@ -55,4 +55,4 @@
<reg name="frm" bitsize="32" type="int" regnum="67"/>
<reg name="fcsr" bitsize="32" type="int" regnum="68"/>
<reg name="placeholder" bitsize="32" type="int" regnum="69"/>
</feature>
</feature>

2
src/arch/riscv/gdb-xml/riscv.xml
View File

@@ -10,4 +10,4 @@
<xi:include href="riscv-64bit-cpu.xml"/>
<xi:include href="riscv-64bit-fpu.xml"/>
<xi:include href="riscv-64bit-csr.xml"/>
</target>
</target>

2
src/arch/riscv/isa/bitfields.isa
View File

@@ -128,4 +128,4 @@ def bitfield M5FUNC <31:25>;
def bitfield BIT24 <24>;
def bitfield RNUM <23:20>;
def bitfield KFUNCT5 <29:25>;
def bitfield BS <31:30>;
def bitfield BS <31:30>;

2
src/arch/sparc/isa/base.isa
View File

@@ -132,5 +132,3 @@ output exec {{
}
}
}};

1
src/arch/sparc/isa/formats/branch.isa
View File

@@ -187,4 +187,3 @@ def format BranchSplit(code=default_branch_code,
decode_block) = doUncondBranch(name, Name,
"BranchSplit", code, annul_code, opt_flags)
}};

1
src/arch/sparc/isa/formats/formats.isa
View File

@@ -51,4 +51,3 @@
// Include the branch format
##include "branch.isa"

1
src/arch/sparc/isa/formats/integerop.isa
View File

@@ -162,4 +162,3 @@ def format SetHi(code, *opt_flags) {{
exec_output = IntOpExecute.subst(iop)
decode_block = SetHiDecode.subst(iop)
}};

1
src/arch/sparc/isa/formats/mem/basicmem.isa
View File

@@ -166,4 +166,3 @@ def format TwinLoad(code, *opt_flags) {{
AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
name, Name, "EXT_ASI", opt_flags)
}};

2
src/arch/sparc/isa/formats/mem/swap.isa
View File

@@ -174,5 +174,3 @@ def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{
decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
name, Name, flags, ["IsStoreConditional"], postacc_code)
}};

1
src/arch/sparc/isa/formats/priv.isa
View File

@@ -133,4 +133,3 @@ def format HPriv(code, check_tl=false, *opt_flags) {{
doPrivFormat(code, check_code, name, Name, opt_flags,
check_tl=(check_tl != 'false'))
}};

1
src/arch/sparc/isa/formats/unimp.isa
View File

@@ -40,4 +40,3 @@ def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

1
src/arch/x86/isa/formats/cpuid.isa
View File

@@ -85,4 +85,3 @@ def format CPUIDInst(code, *opt_flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = CPUIDExecute.subst(iop)
}};

1
src/arch/x86/isa/formats/error.isa
View File

@@ -54,4 +54,3 @@ def format M5InternalError(error_message) {{
iop.message = error_message
decode_block = ErrorDecode.subst(iop)
}};

1
src/arch/x86/isa/formats/monitor_mwait.isa
View File

@@ -122,4 +122,3 @@ def format MwaitInst(code, *opt_flags) {{
exec_output += MwaitInitiateAcc.subst(iop)
exec_output += MwaitCompleteAcc.subst(iop)
}};

1
src/arch/x86/isa/formats/nop.isa
View File

@@ -84,4 +84,3 @@ def format NopInst(*opt_flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = NopExecute.subst(iop)
}};

1
src/arch/x86/isa/formats/syscall.isa
View File

@@ -88,4 +88,3 @@ def format SyscallInst(code, *opt_flags) {{
decode_block = BasicDecode.subst(iop)
exec_output = SyscallExecute.subst(iop)
}};

1
src/arch/x86/isa/formats/unimp.isa
View File

@@ -149,4 +149,3 @@ def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

1
src/base/bitfield.test.cc
View File

@@ -456,4 +456,3 @@ TEST(BitfieldTest, CountLeadingZero64AllZeros)
uint64_t value = 0;
EXPECT_EQ(64, clz64(value));
}

1
src/base/filters/multi_bit_sel_bloom_filter.cc
View File

@@ -100,4 +100,3 @@ MultiBitSel::hash(Addr addr, int hash_number) const
} // namespace bloom_filter
} // namespace gem5

2
src/cpu/testers/gpu_ruby_test/README
View File

@@ -124,4 +124,4 @@ For more detail, please see the following paper:
T. Ta, X. Zhang, A. Gutierrez and B. M. Beckmann, "Autonomous Data-Race-Free
GPU Testing," 2019 IEEE International Symposium on Workload Characterization
(IISWC), Orlando, FL, USA, 2019, pp. 81-92, doi:
10.1109/IISWC47752.2019.9042019.
10.1109/IISWC47752.2019.9042019.

1
src/cpu/testers/traffic_gen/SConscript
View File

@@ -68,4 +68,3 @@ if env['USE_PYTHON']:
SimObject('TrafficGen.py', sim_objects=['TrafficGen'], tags='protobuf')
Source('trace_gen.cc', tags='protobuf')
Source('traffic_gen.cc', tags='protobuf')

2
src/cpu/trace/TraceCPU.py
View File

@@ -39,7 +39,7 @@ from m5.objects.BaseCPU import BaseCPU
class TraceCPU(BaseCPU):
"""Trace CPU model which replays traces generated in a prior simulation
using DerivO3CPU or its derived classes. It interfaces with L1 caches.
using DerivO3CPU or its derived classes. It interfaces with L1 caches.
"""
type = "TraceCPU"

1
src/dev/amdgpu/hwreg_defines.hh
View File

@@ -72,4 +72,3 @@ enum amdgpu_hwreg
} // namespace gem5
#endif // __DEV_GPU_HWREG_DEFINES_H__

52
src/dev/arm/GenericTimer.py
View File

@@ -43,12 +43,12 @@ from m5.util.fdthelper import FdtNode, FdtProperty, FdtPropertyWords, FdtState
class SystemCounter(SimObject):
"""
Shared by both PE-implementations and memory-mapped timers. It provides a
uniform view of system time through its counter value.
Shared by both PE-implementations and memory-mapped timers. It provides a
uniform view of system time through its counter value.
Reference:
Arm ARM (ARM DDI 0487E.a)
D11.1.2 - The system counter
Reference:
Arm ARM (ARM DDI 0487E.a)
D11.1.2 - The system counter
"""
type = "SystemCounter"
@@ -71,14 +71,14 @@ Reference:
class GenericTimer(SimObject):
"""
Architected timers per PE in the system. Each of them provides a physical
counter, a virtual counter and several timers accessible from different
exception levels and security states.
Architected timers per PE in the system. Each of them provides a physical
counter, a virtual counter and several timers accessible from different
exception levels and security states.
Reference:
Arm ARM (ARM DDI 0487E.a)
D11.2 - The AArch64 view of the Generic Timer
G6.2 - The AArch32 view of the Generic Timer
Reference:
Arm ARM (ARM DDI 0487E.a)
D11.2 - The AArch64 view of the Generic Timer
G6.2 - The AArch32 view of the Generic Timer
"""
type = "GenericTimer"
@@ -135,12 +135,12 @@ Reference:
class GenericTimerFrame(PioDevice):
"""
Memory-mapped timer frame implementation. Controlled from GenericTimerMem,
may be used by peripherals without a system register interface.
Memory-mapped timer frame implementation. Controlled from GenericTimerMem,
may be used by peripherals without a system register interface.
Reference:
Arm ARM (ARM DDI 0487E.a)
I2.3.2 - The CNTBaseN and CNTEL0BaseN frames
Reference:
Arm ARM (ARM DDI 0487E.a)
I2.3.2 - The CNTBaseN and CNTEL0BaseN frames
"""
type = "GenericTimerFrame"
@@ -178,16 +178,16 @@ Reference:
class GenericTimerMem(PioDevice):
"""
System level implementation. It provides three main components:
- Memory-mapped counter module: controls the system timer through the
CNTControlBase frame, and provides its value through the CNTReadBase frame
- Memory-mapped timer control module: controls the memory-mapped timers
- Memory-mapped timers: implementations of the GenericTimer for system
peripherals
System level implementation. It provides three main components:
- Memory-mapped counter module: controls the system timer through the
CNTControlBase frame, and provides its value through the CNTReadBase frame
- Memory-mapped timer control module: controls the memory-mapped timers
- Memory-mapped timers: implementations of the GenericTimer for system
peripherals
Reference:
Arm ARM (ARM DDI 0487E.a)
I2 - System Level Implementation of the Generic Timer
Reference:
Arm ARM (ARM DDI 0487E.a)
I2 - System Level Implementation of the Generic Timer
"""
type = "GenericTimerMem"

292
src/dev/arm/RealView.py
View File

@@ -339,9 +339,9 @@ class RealViewTemperatureSensor(SimObject):
class VExpressMCC(SubSystem):
"""ARM V2M-P1 Motherboard Configuration Controller
This subsystem describes a subset of the devices that sit behind the
motherboard configuration controller on the the ARM Motherboard
Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
This subsystem describes a subset of the devices that sit behind the
motherboard configuration controller on the the ARM Motherboard
Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
"""
class Osc(RealViewOsc):
@@ -380,9 +380,9 @@ Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
class CoreTile2A15DCC(SubSystem):
"""ARM CoreTile Express A15x2 Daughterboard Configuration Controller
This subsystem describes a subset of the devices that sit behind the
daughterboard configuration controller on a CoreTile Express A15x2. See
ARM DUI 0604E for details.
This subsystem describes a subset of the devices that sit behind the
daughterboard configuration controller on a CoreTile Express A15x2. See
ARM DUI 0604E for details.
"""
class Osc(RealViewOsc):
@@ -491,10 +491,10 @@ class Sp804(AmbaPioDevice):
class Sp805(AmbaIntDevice):
"""
Arm Watchdog Module (SP805)
Reference:
Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
Doc. ID: ARM DDI 0270B
Arm Watchdog Module (SP805)
Reference:
Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
Doc. ID: ARM DDI 0270B
"""
type = "Sp805"
@@ -746,10 +746,10 @@ class MmioSRAM(ParentMem):
class FVPBasePwrCtrl(BasicPioDevice):
"""
Based on Fast Models Base_PowerController v11.8
Reference:
Fast Models Reference Manual - Section 7.7.2 - Version 11.8
Document ID: 100964_1180_00_en
Based on Fast Models Base_PowerController v11.8
Reference:
Fast Models Reference Manual - Section 7.7.2 - Version 11.8
Document ID: 100964_1180_00_en
"""
type = "FVPBasePwrCtrl"
@@ -1100,148 +1100,148 @@ class VExpress_EMM64(VExpress_EMM):
class VExpress_GEM5_Base(RealView):
"""
The VExpress gem5 memory map is loosely based on a modified
Versatile Express RS1 memory map.
The VExpress gem5 memory map is loosely based on a modified
Versatile Express RS1 memory map.
The gem5 platform has been designed to implement a subset of the
original Versatile Express RS1 memory map. Off-chip peripherals should,
when possible, adhere to the Versatile Express memory map. Non-PCI
off-chip devices that are gem5-specific should live in the CS5 memory
space to avoid conflicts with existing devices that we might want to
model in the future. Such devices should normally have interrupts in
the gem5-specific SPI range.
The gem5 platform has been designed to implement a subset of the
original Versatile Express RS1 memory map. Off-chip peripherals should,
when possible, adhere to the Versatile Express memory map. Non-PCI
off-chip devices that are gem5-specific should live in the CS5 memory
space to avoid conflicts with existing devices that we might want to
model in the future. Such devices should normally have interrupts in
the gem5-specific SPI range.
On-chip peripherals are loosely modeled after the ARM CoreTile Express
A15x2 memory and interrupt map. In particular, the GIC and
Generic Timer have the same interrupt lines and base addresses. Other
on-chip devices are gem5 specific.
On-chip peripherals are loosely modeled after the ARM CoreTile Express
A15x2 memory and interrupt map. In particular, the GIC and
Generic Timer have the same interrupt lines and base addresses. Other
on-chip devices are gem5 specific.
Unlike the original Versatile Express RS2 extended platform, gem5 implements a
large contigious DRAM space, without aliases or holes, starting at the
2GiB boundary. This means that PCI memory is limited to 1GiB.
Unlike the original Versatile Express RS2 extended platform, gem5 implements a
large contigious DRAM space, without aliases or holes, starting at the
2GiB boundary. This means that PCI memory is limited to 1GiB.
References:
References:
Technical Reference Manuals:
Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J
Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
Technical Reference Manuals:
Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J
Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
Official Linux device tree specifications:
V2M-P1 - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
Official Linux device tree specifications:
V2M-P1 - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
Memory map:
Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
Daughterboard (global)
Section 3.2.1 - Table 3-1 - Daughterboard memory map
On-chip
Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral
memory map
Interrupts:
Armv8-A Foundation Platform - User Guide - Version 11.8
Document ID: 100961_1180_00_en
Memory map:
Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
Daughterboard (global)
Section 3.2.1 - Table 3-1 - Daughterboard memory map
On-chip
Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral
memory map
0x00000000-0x03ffffff: Boot memory (CS0)
0x04000000-0x07ffffff: Trusted Memory/Reserved
0x04000000-0x0403FFFF: 256kB Trusted SRAM
0x06000000-0x07ffffff: 32MB Trusted DRAM
0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
0x10000000-0x1000ffff: gem5 energy controller
0x10010000-0x1001ffff: gem5 pseudo-ops
0x10020000-0x1002ffff: gem5 MHU
0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
0x18000000-0x1bffffff: Off-chip, Peripherals, CS2
0x18000000-0x19ffffff: VRAM
0x1a000000-0x1bffffff: Reserved
0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
0x1c060000-0x1c06ffff: KMI0 (keyboard)
0x1c070000-0x1c07ffff: KMI1 (mouse)
0x1c090000-0x1c09ffff: UART0
0x1c0a0000-0x1c0affff: UART1
0x1c0b0000-0x1c0bffff: UART2
0x1c0c0000-0x1c0cffff: UART3
0x1c0f0000-0x1c0fffff: Watchdog (SP805)
0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
0x1c170000-0x1c17ffff: RTC
0x20000000-0x3fffffff: On-chip peripherals:
0x2a430000-0x2a43ffff: System Counter (control)
0x2a490000-0x2a49ffff: Trusted Watchdog (SP805)
0x2a800000-0x2a800fff: System Counter (read)
0x2a810000-0x2a810fff: System Timer (control)
0x2a820000-0x2a820fff: System Timer (frame 0)
0x2a830000-0x2a830fff: System Timer (frame 1)
0x2b000000-0x2b00ffff: HDLCD
0x2b060000-0x2b060fff: System Watchdog (SP805)
0x2b400000-0x2b41ffff: SMMUv3
0x2c001000-0x2c001fff: GIC (distributor)
0x2c002000-0x2c003fff: GIC (CPU interface)
0x2c004000-0x2c005fff: vGIC (HV)
0x2c006000-0x2c007fff: vGIC (VCPU)
0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
0x2d000000-0x2d00ffff: GPU (reserved)
0x2e000000-0x2e007fff: Non-trusted SRAM
0x2f000000-0x2fffffff: PCI IO space
0x30000000-0x3fffffff: PCI config space
0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
0x80000000-X: DRAM
Interrupts:
Armv8-A Foundation Platform - User Guide - Version 11.8
Document ID: 100961_1180_00_en
Memory map:
0x00000000-0x03ffffff: Boot memory (CS0)
0x04000000-0x07ffffff: Trusted Memory/Reserved
0x04000000-0x0403FFFF: 256kB Trusted SRAM
0x06000000-0x07ffffff: 32MB Trusted DRAM
0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
0x10000000-0x1000ffff: gem5 energy controller
0x10010000-0x1001ffff: gem5 pseudo-ops
0x10020000-0x1002ffff: gem5 MHU
0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
0x18000000-0x1bffffff: Off-chip, Peripherals, CS2
0x18000000-0x19ffffff: VRAM
0x1a000000-0x1bffffff: Reserved
0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
0x1c060000-0x1c06ffff: KMI0 (keyboard)
0x1c070000-0x1c07ffff: KMI1 (mouse)
0x1c090000-0x1c09ffff: UART0
0x1c0a0000-0x1c0affff: UART1
0x1c0b0000-0x1c0bffff: UART2
0x1c0c0000-0x1c0cffff: UART3
0x1c0f0000-0x1c0fffff: Watchdog (SP805)
0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
0x1c170000-0x1c17ffff: RTC
0x20000000-0x3fffffff: On-chip peripherals:
0x2a430000-0x2a43ffff: System Counter (control)
0x2a490000-0x2a49ffff: Trusted Watchdog (SP805)
0x2a800000-0x2a800fff: System Counter (read)
0x2a810000-0x2a810fff: System Timer (control)
0x2a820000-0x2a820fff: System Timer (frame 0)
0x2a830000-0x2a830fff: System Timer (frame 1)
0x2b000000-0x2b00ffff: HDLCD
0x2b060000-0x2b060fff: System Watchdog (SP805)
0x2b400000-0x2b41ffff: SMMUv3
0x2c001000-0x2c001fff: GIC (distributor)
0x2c002000-0x2c003fff: GIC (CPU interface)
0x2c004000-0x2c005fff: vGIC (HV)
0x2c006000-0x2c007fff: vGIC (VCPU)
0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
0x2d000000-0x2d00ffff: GPU (reserved)
0x2e000000-0x2e007fff: Non-trusted SRAM
0x2f000000-0x2fffffff: PCI IO space
0x30000000-0x3fffffff: PCI config space
0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
0x80000000-X: DRAM
Interrupts:
0- 15: Software generated interrupts (SGIs)
16- 31: On-chip private peripherals (PPIs)
19 : generic_timer (virt sec EL2)
20 : generic_timer (phys sec EL2)
25 : vgic
26 : generic_timer (phys non-sec EL2)
27 : generic_timer (virt EL1)
28 : generic_timer (virt non-sec EL2)
29 : generic_timer (phys EL3)
30 : generic_timer (phys EL1)
31 : Reserved (Legacy IRQ)
32- 95: Mother board peripherals (SPIs)
32 : Watchdog (SP805)
33 : Reserved (IOFPGA SW int)
34-35: Reserved (SP804)
36 : RTC
37-40: uart0-uart3
41-42: Reserved (PL180)
43 : Reserved (AACI)
44-45: kmi0-kmi1
46 : Reserved (CLCD)
47 : Reserved (Ethernet)
48 : Reserved (USB)
56 : Trusted Watchdog (SP805)
57 : System timer0 (phys)
58 : System timer1 (phys)
95-255: On-chip interrupt sources (we use these for
gem5-specific devices, SPIs)
74 : VirtIO (gem5/FM extension)
75 : VirtIO (gem5/FM extension)
95 : HDLCD
96- 98: GPU (reserved)
100-103: PCI
130 : System Watchdog (SP805)
256-319: MSI frame 0 (gem5-specific, SPIs)
320-511: Unused
0- 15: Software generated interrupts (SGIs)
16- 31: On-chip private peripherals (PPIs)
19 : generic_timer (virt sec EL2)
20 : generic_timer (phys sec EL2)
25 : vgic
26 : generic_timer (phys non-sec EL2)
27 : generic_timer (virt EL1)
28 : generic_timer (virt non-sec EL2)
29 : generic_timer (phys EL3)
30 : generic_timer (phys EL1)
31 : Reserved (Legacy IRQ)
32- 95: Mother board peripherals (SPIs)
32 : Watchdog (SP805)
33 : Reserved (IOFPGA SW int)
34-35: Reserved (SP804)
36 : RTC
37-40: uart0-uart3
41-42: Reserved (PL180)
43 : Reserved (AACI)
44-45: kmi0-kmi1
46 : Reserved (CLCD)
47 : Reserved (Ethernet)
48 : Reserved (USB)
56 : Trusted Watchdog (SP805)
57 : System timer0 (phys)
58 : System timer1 (phys)
95-255: On-chip interrupt sources (we use these for
gem5-specific devices, SPIs)
74 : VirtIO (gem5/FM extension)
75 : VirtIO (gem5/FM extension)
95 : HDLCD
96- 98: GPU (reserved)
100-103: PCI
130 : System Watchdog (SP805)
256-319: MSI frame 0 (gem5-specific, SPIs)
320-511: Unused
"""

1
src/dev/arm/a9scu.hh
View File

@@ -84,4 +84,3 @@ class A9SCU : public BasicPioDevice
} // namespace gem5
#endif // __DEV_ARM_A9SCU_HH__

22
src/dev/hsa/hsa.h
View File

@@ -2,24 +2,24 @@
//
// The University of Illinois/NCSA
// Open Source License (NCSA)
//
//
// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
//
//
// Developed by:
//
//
// AMD Research and AMD HSA Software Development
//
//
// Advanced Micro Devices, Inc.
//
//
// www.amd.com
//
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to
// deal with the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimers.
// - Redistributions in binary form must reproduce the above copyright
@@ -29,7 +29,7 @@
// nor the names of its contributors may be used to endorse or promote
// products derived from this Software without specific prior written
// permission.
//
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -632,7 +632,7 @@ hsa_status_t HSA_API hsa_system_major_extension_supported(
uint16_t version_major,
uint16_t *version_minor,
bool* result);
/**
* @deprecated
@@ -711,7 +711,7 @@ hsa_status_t HSA_API hsa_system_get_major_extension_table(
uint16_t extension,
uint16_t version_major,
size_t table_length,
void *table);
void *table);
/**
* @brief Struct containing an opaque handle to an agent, a device that participates in
@@ -1291,7 +1291,7 @@ hsa_status_t HSA_API hsa_agent_major_extension_supported(
uint16_t version_major,
uint16_t *version_minor,
bool* result);
/** @} */

1
src/dev/lupio/lupio_ipi.cc
View File

@@ -148,4 +148,3 @@ LupioIPI::write(PacketPtr pkt)
return pioDelay;
}
} // namespace gem5

1
src/dev/lupio/lupio_ipi.hh
View File

@@ -96,4 +96,3 @@ class LupioIPI : public BasicPioDevice
} // namespace gem5
#endif // __DEV_LUPIO_LUPIO_IPI_HH

1
src/dev/ps2/mouse.hh
View File

@@ -81,4 +81,3 @@ class PS2Mouse : public Device
} // namespace gem5
#endif // __DEV_PS2_MOUSE_hH__

21
src/dev/riscv/HiFive.py
View File

@@ -142,13 +142,11 @@ class HiFive(Platform):
terminal = Terminal()
def _on_chip_devices(self):
"""Returns a list of on-chip peripherals
"""
"""Returns a list of on-chip peripherals"""
return [self.clint, self.plic]
def _off_chip_devices(self):
"""Returns a list of off-chip peripherals
"""
"""Returns a list of off-chip peripherals"""
devices = [self.uart]
if hasattr(self, "disk"):
devices.append(self.disk)
@@ -158,7 +156,7 @@ class HiFive(Platform):
def _on_chip_ranges(self):
"""Returns a list of on-chip peripherals
address range
address range
"""
return [
AddrRange(dev.pio_addr, size=dev.pio_size)
@@ -167,7 +165,7 @@ class HiFive(Platform):
def _off_chip_ranges(self):
"""Returns a list of off-chip peripherals
address range
address range
"""
return [
AddrRange(dev.pio_addr, size=dev.pio_size)
@@ -175,8 +173,7 @@ class HiFive(Platform):
]
def attachPlic(self):
"""Count number of PLIC interrupt sources
"""
"""Count number of PLIC interrupt sources"""
plic_srcs = [
self.uart_int_id,
self.pci_host.int_base + self.pci_host.int_count,
@@ -188,21 +185,21 @@ class HiFive(Platform):
def attachOnChipIO(self, bus):
"""Attach on-chip IO devices, needs modification
to support DMA
to support DMA
"""
for device in self._on_chip_devices():
device.pio = bus.mem_side_ports
def attachOffChipIO(self, bus):
"""Attach off-chip IO devices, needs modification
to support DMA
to support DMA
"""
for device in self._off_chip_devices():
device.pio = bus.mem_side_ports
def setNumCores(self, num_cpu):
""" Sets the PLIC and CLINT to have the right number of threads and
contexts. Assumes that the cores have a single hardware thread.
"""Sets the PLIC and CLINT to have the right number of threads and
contexts. Assumes that the cores have a single hardware thread.
"""
self.plic.n_contexts = num_cpu * 2
self.clint.num_threads = num_cpu

1
src/dev/rtcreg.h
View File

@@ -52,4 +52,3 @@ static const int RTC_STAT_REGB = 0x0B;
static const int RTC_STAT_REGC = 0x0C;
static const int RTC_STAT_REGD = 0x0D;

2
src/mem/SysBridge.py
View File

@@ -29,7 +29,7 @@ from m5.SimObject import SimObject
class SysBridge(SimObject):
"""Use this bridge to connect the memory systems belonging to two different
Systems SimObjects. See the header file for more information."""
Systems SimObjects. See the header file for more information."""
type = "SysBridge"
cxx_header = "mem/sys_bridge.hh"

1
src/mem/cache/SConscript vendored
View File

@@ -56,4 +56,3 @@ DebugFlag('HWPrefetchQueue')
# it explicitly even above and beyond CacheAll.
CompoundFlag('CacheAll', ['Cache', 'CacheComp', 'CachePort', 'CacheRepl',
'CacheVerbose', 'HWPrefetch', 'MSHR'])

2
src/mem/port_terminator.cc
View File

@@ -54,4 +54,4 @@ PortTerminator::getPort(const std::string &if_name, PortID idx)
}
}
}
}

1
src/mem/ruby/network/fault_model/SConscript
View File

@@ -38,4 +38,3 @@ if env['CONF']['PROTOCOL'] == 'None':
SimObject('FaultModel.py', sim_objects=['FaultModel'])
Source('FaultModel.cc')

1
src/mem/ruby/network/garnet/README.txt
View File

@@ -76,4 +76,3 @@ instantiated, then the Network Brisge takes over the flit in HeteroGarnet.
serializing or deserializing the flits
* Check if CDC is enabled and schedule all the flits according
to the consumers clock domain.

6
src/mem/ruby/protocol/MI_example-dma.sm
View File

@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
machine(MachineType:DMA, "DMA Controller")
machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
@@ -134,7 +134,7 @@ machine(MachineType:DMA, "DMA Controller")
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(requestToDir_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
@@ -149,7 +149,7 @@ machine(MachineType:DMA, "DMA Controller")
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(requestToDir_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;

2
src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
View File

@@ -2978,5 +2978,3 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
// END TRANSITIONS
}

2
src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
View File

@@ -3008,5 +3008,3 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
// END TRANSITIONS
}

1
src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
View File

@@ -1371,4 +1371,3 @@ machine(MachineType:RegionBuffer, "Region Buffer for AMD_Base-like protocol")
}
}

2
src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
View File

@@ -1180,5 +1180,3 @@ machine(MachineType:RegionDir, "Region Directory for AMD_Base-like protocol")
}
}

4
src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
View File

@@ -51,7 +51,7 @@ machine(MachineType:L1Cache, "Token protocol")
// Message Queues
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank
MessageBuffer * responseFromL1Cache, network="To", virtual_network="4",
vnet_type="response";
@@ -60,7 +60,7 @@ machine(MachineType:L1Cache, "Token protocol")
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer * requestFromL1Cache, network="To", virtual_network="1",
vnet_type="request";
// To this node's L1 cache FROM the network
// a L2 bank -> this L1

62
src/mem/ruby/protocol/MOESI_hammer-dir.sm
View File

@@ -26,11 +26,11 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* AMD's contributions to the MOESI hammer protocol do not constitute an
* AMD's contributions to the MOESI hammer protocol do not constitute an
* endorsement of its similarity to any AMD products.
*/
machine(MachineType:Directory, "AMD Hammer-like protocol")
machine(MachineType:Directory, "AMD Hammer-like protocol")
: DirectoryMemory * directory;
CacheMemory * probeFilter;
Cycles from_memory_controller_latency := 2;
@@ -44,7 +44,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
MessageBuffer * responseFromDir, network="To", virtual_network="4",
vnet_type="response";
// For a finite buffered network, note that the DMA response network only
// For a finite buffered network, note that the DMA response network only
// works at this relatively lower numbered (lower priority) virtual network
// because the trigger queue decouples cache responses from DMA responses.
MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
@@ -107,7 +107,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
enumeration(Event, desc="Directory events") {
GETX, desc="A GETX arrives";
GETS, desc="A GETS arrives";
PUT, desc="A PUT arrives";
PUT, desc="A PUT arrives";
Unblock, desc="An unblock message arrives";
UnblockS, desc="An unblock message arrives";
UnblockM, desc="An unblock message arrives";
@@ -244,7 +244,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
assert(is_valid(pf_entry) == false);
}
}
if (state == State:E || state == State:NX || state == State:NO || state == State:S ||
if (state == State:E || state == State:NX || state == State:NO || state == State:S ||
state == State:O) {
assert(is_valid(tbe) == false);
}
@@ -456,17 +456,17 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
}
// Actions
action(r_setMRU, "\rr", desc="manually set the MRU bit for pf entry" ) {
if (probe_filter_enabled || full_bit_dir_enabled) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
probeFilter.setMRU(address);
}
}
action(auno_assertUnblockerNotOwner, "auno", desc="assert unblocker not owner") {
if (probe_filter_enabled || full_bit_dir_enabled) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
peek(unblockNetwork_in, ResponseMsg) {
assert(cache_entry.Owner != in_msg.Sender);
if (full_bit_dir_enabled) {
@@ -478,7 +478,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(uo_updateOwnerIfPf, "uo", desc="update owner") {
if (probe_filter_enabled || full_bit_dir_enabled) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
peek(unblockNetwork_in, ResponseMsg) {
cache_entry.Owner := in_msg.Sender;
if (full_bit_dir_enabled) {
@@ -637,7 +637,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
tbe.Acks := 1;
}
}
}
}
action(saa_setAcksToAllIfPF, "saa", desc="Non-forwarded request, set the ack amount to all") {
assert(is_valid(tbe));
@@ -647,7 +647,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
} else {
tbe.Acks := 1;
}
}
}
action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
peek(responseToDir_in, ResponseMsg) {
@@ -655,8 +655,8 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
assert(in_msg.Acks > 0);
DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
//
// Note that cache data responses will have an ack count of 2. However,
// directory DMA requests must wait for acks from all LLC caches, so
// Note that cache data responses will have an ack count of 2. However,
// directory DMA requests must wait for acks from all LLC caches, so
// only decrement by 1.
//
if ((in_msg.Type == CoherenceResponseType:DATA_SHARED) ||
@@ -763,7 +763,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
//
// we send the entire data block and rely on the dma controller to
// we send the entire data block and rely on the dma controller to
// split it up if need be
//
out_msg.DataBlk := in_msg.DataBlk;
@@ -781,7 +781,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
//
// we send the entire data block and rely on the dma controller to
// we send the entire data block and rely on the dma controller to
// split it up if need be
//
out_msg.DataBlk := tbe.DataBlk;
@@ -797,7 +797,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
out_msg.Destination.add(tbe.DmaRequestor);
out_msg.Destination.add(tbe.DmaRequestor);
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -935,7 +935,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(io_invalidateOwnerRequest, "io", desc="invalidate all copies") {
if (machineCount(MachineType:L1Cache) > 1) {
enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
out_msg.addr := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := machineID;
@@ -1015,7 +1015,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.InitialRequestTime := zero_time();
out_msg.ForwardRequestTime := curCycle();
}
}
}
}
@@ -1024,7 +1024,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
if (probe_filter_enabled || full_bit_dir_enabled) {
peek(requestQueue_in, RequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
out_msg.addr := address;
out_msg.Type := in_msg.Type;
out_msg.Requestor := in_msg.Requestor;
@@ -1034,7 +1034,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
out_msg.ForwardRequestTime := curCycle();
}
}
}
} else {
peek(requestQueue_in, RequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
@@ -1099,7 +1099,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
// itself
//
out_msg.Requestor := machineID;
out_msg.Destination.broadcast(MachineType:L1Cache);
out_msg.Destination.broadcast(MachineType:L1Cache);
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
}
}
@@ -1118,7 +1118,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
// itself
//
out_msg.Requestor := machineID;
out_msg.Destination.broadcast(MachineType:L1Cache);
out_msg.Destination.broadcast(MachineType:L1Cache);
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
}
}
@@ -1132,7 +1132,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") {
peek(unblockNetwork_in, ResponseMsg) {
APPEND_TRANSITION_COMMENT(in_msg.Sender);
}
}
unblockNetwork_in.dequeue(clockEdge());
}
@@ -1155,7 +1155,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") {
peek(dmaRequestQueue_in, DMARequestMsg) {
APPEND_TRANSITION_COMMENT(in_msg.Requestor);
}
}
stall_and_wait(dmaRequestQueue_in, address);
}
@@ -1184,7 +1184,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(ano_assertNotOwner, "ano", desc="Assert that request is not current owner") {
if (probe_filter_enabled || full_bit_dir_enabled) {
peek(requestQueue_in, RequestMsg) {
assert(is_valid(cache_entry));
assert(is_valid(cache_entry));
assert(cache_entry.Owner != in_msg.Requestor);
}
}
@@ -1263,7 +1263,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
action(z_stallAndWaitRequest, "z", desc="Recycle the request queue") {
peek(requestQueue_in, RequestMsg) {
APPEND_TRANSITION_COMMENT(in_msg.Requestor);
}
}
stall_and_wait(requestQueue_in, address);
}
@@ -1467,7 +1467,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
//
// note that the PUT requestor may not be the current owner if an invalidate
// raced with PUT
//
//
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
@@ -1485,9 +1485,9 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
}
// Blocked transient states
transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
{GETS, GETX, GETF, PUT, Pf_Replacement}) {
z_stallAndWaitRequest;
}
@@ -1508,9 +1508,9 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
z_stallAndWaitRequest;
}
transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
{DMA_READ, DMA_WRITE}) {
zd_stallAndWaitDMARequest;
}

6
src/mem/ruby/protocol/MOESI_hammer-dma.sm
View File

@@ -27,7 +27,7 @@
*/
machine(MachineType:DMA, "DMA Controller")
machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
@@ -134,7 +134,7 @@ machine(MachineType:DMA, "DMA Controller")
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(requestToDir_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
@@ -149,7 +149,7 @@ machine(MachineType:DMA, "DMA Controller")
peek(dmaRequestQueue_in, SequencerMsg) {
enqueue(requestToDir_out, DMARequestMsg, request_latency) {
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;

2
src/mem/ruby/protocol/MOESI_hammer-msg.sm
View File

@@ -25,7 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* AMD's contributions to the MOESI hammer protocol do not constitute an
* AMD's contributions to the MOESI hammer protocol do not constitute an
* endorsement of its similarity to any AMD products.
*/

1
src/mem/ruby/protocol/SConscript
View File

@@ -118,4 +118,3 @@ for f in nodes:
# for it to contain a single SimObject with the same name.
assert(filename.endswith('_Controller.py'))
SimObject(f, sim_objects=[os.path.splitext(filename)[0]])

2
src/mem/ruby/protocol/chi/CHI-dvm-misc-node-transitions.sm
View File

@@ -181,4 +181,4 @@ transition(DvmOp_Complete, Final, Unallocated) {
Pop_TriggerQueue; // "Final" event is applied from the trigger queue
Finalize_DeallocateRequest; // Deallocate the DVM TBE
}
}

2
src/mem/ruby/protocol/chi/CHI-msg.sm
View File

@@ -247,5 +247,3 @@ structure(CHIDataMsg, desc="", interface="Message") {
return testAndWrite(addr, dataBlk, pkt);
}
}

2
src/mem/ruby/protocol/chi/CHI.slicc
View File

@@ -4,4 +4,4 @@ include "RubySlicc_interfaces.slicc";
include "CHI-msg.sm";
include "CHI-cache.sm";
include "CHI-mem.sm";
include "CHI-dvm-misc-node.sm";
include "CHI-dvm-misc-node.sm";

1
src/mem/ruby/slicc_interface/RubySlicc_includes.hh
View File

@@ -33,4 +33,3 @@
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_INCLUDES_HH__

52
src/mem/slicc/parser.py
View File

@@ -381,8 +381,8 @@ class SLICC(Grammar):
def p_type_member__0(self, p):
"""type_member : obj_decl
| func_decl
| func_def"""
| func_decl
| func_def"""
p[0] = p[1]
# Member / Variable declarations
@@ -417,12 +417,12 @@ class SLICC(Grammar):
def p_func_decl__0(self, p):
"""func_decl : void ident '(' params ')' pairs SEMI
| type ident '(' params ')' pairs SEMI"""
| type ident '(' params ')' pairs SEMI"""
p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], None)
def p_func_decl__1(self, p):
"""func_decl : void ident '(' types ')' pairs SEMI
| type ident '(' types ')' pairs SEMI"""
| type ident '(' types ')' pairs SEMI"""
p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], None)
def p_decl__func_def(self, p):
@@ -431,7 +431,7 @@ class SLICC(Grammar):
def p_func_def__0(self, p):
"""func_def : void ident '(' params ')' pairs statements
| type ident '(' params ')' pairs statements"""
| type ident '(' params ')' pairs statements"""
p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], p[7])
# Enum fields
@@ -545,7 +545,7 @@ class SLICC(Grammar):
def p_identx__multiple_1(self, p):
"""identx : ident SEMI identx
| ident ',' identx"""
| ident ',' identx"""
p[0] = [p[1]] + p[3]
def p_identx__multiple_2(self, p):
@@ -562,7 +562,7 @@ class SLICC(Grammar):
def p_ident_or_star(self, p):
"""ident_or_star : ident
| STAR"""
| STAR"""
p[0] = p[1]
# Pair and pair lists
@@ -586,8 +586,8 @@ class SLICC(Grammar):
def p_pair__assign(self, p):
"""pair : ident '=' STRING
| ident '=' ident
| ident '=' NUMBER"""
| ident '=' ident
| ident '=' NUMBER"""
p[0] = ast.PairAST(self, p[1], p[3])
def p_pair__literal(self, p):
@@ -757,28 +757,28 @@ class SLICC(Grammar):
def p_expr__binary_op(self, p):
"""expr : expr STAR expr
| expr SLASH expr
| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LT expr
| expr GT expr
| expr LE expr
| expr GE expr
| expr EQ expr
| expr NE expr
| expr AND expr
| expr OR expr
| expr RIGHTSHIFT expr
| expr LEFTSHIFT expr"""
| expr SLASH expr
| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LT expr
| expr GT expr
| expr LE expr
| expr GE expr
| expr EQ expr
| expr NE expr
| expr AND expr
| expr OR expr
| expr RIGHTSHIFT expr
| expr LEFTSHIFT expr"""
p[0] = ast.InfixOperatorExprAST(self, p[1], p[2], p[3])
# FIXME - unary not
def p_expr__unary_op(self, p):
"""expr : NOT expr
| INCR expr
| DECR expr
| DASH expr %prec UMINUS"""
| INCR expr
| DECR expr
| DASH expr %prec UMINUS"""
p[0] = ast.PrefixOperatorExprAST(self, p[1], p[2])
def p_expr__parens(self, p):

2
src/mem/slicc/symbols/StateMachine.py
View File

@@ -920,7 +920,7 @@ $c_ident::regStats()
AbstractController::regStats();
// For each type of controllers, one controller of that type is picked
// to aggregate stats of all controllers of that type.
// to aggregate stats of all controllers of that type.
if (m_version == 0) {
Profiler *profiler = params().ruby_system->getProfiler();

1
src/proto/inst.proto
View File

@@ -112,4 +112,3 @@ message Inst {
}
repeated MemAccess mem_access = 8;
}

2
src/python/gem5/components/boards/x86_board.py
View File

@@ -105,7 +105,7 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
self.m5ops_base = 0xFFFF0000
def _setup_io_devices(self):
""" Sets up the x86 IO devices.
"""Sets up the x86 IO devices.
Note: This is mostly copy-paste from prior X86 FS setups. Some of it
may not be documented and there may be bugs.

3
src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
View File

@@ -38,8 +38,7 @@ from .abstract_node import TriggerMessageBuffer
class MemoryController(Memory_Controller):
"""A controller that connects to memory
"""
"""A controller that connects to memory"""
_version = 0

4
src/python/gem5/components/memory/dramsim_3.py
View File

@@ -128,7 +128,9 @@ class SingleChannel(AbstractMemorySystem):
self.mem_ctrl.range = ranges[0]
def SingleChannelDDR3_1600(size: Optional[str] = "2048MB",) -> SingleChannel:
def SingleChannelDDR3_1600(
size: Optional[str] = "2048MB",
) -> SingleChannel:
"""
A single channel DDR3_1600.

2
src/python/gem5/components/memory/memory.py
View File

@@ -45,7 +45,7 @@ def _try_convert(val, cls):
def _isPow2(num):
log_num = int(log(num, 2))
if 2 ** log_num != num:
if 2**log_num != num:
return False
else:
return True

16
src/python/gem5/components/memory/multi_channel.py
View File

@@ -34,21 +34,27 @@ from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
from .dram_interfaces.hbm import HBM_1000_4H_1x64
def DualChannelDDR3_1600(size: Optional[str] = None,) -> AbstractMemorySystem:
def DualChannelDDR3_1600(
size: Optional[str] = None,
) -> AbstractMemorySystem:
"""
A dual channel memory system using DDR3_1600_8x8 based DIMM
"""
return ChanneledMemory(DDR3_1600_8x8, 2, 64, size=size)
def DualChannelDDR3_2133(size: Optional[str] = None,) -> AbstractMemorySystem:
def DualChannelDDR3_2133(
size: Optional[str] = None,
) -> AbstractMemorySystem:
"""
A dual channel memory system using DDR3_2133_8x8 based DIMM
"""
return ChanneledMemory(DDR3_2133_8x8, 2, 64, size=size)
def DualChannelDDR4_2400(size: Optional[str] = None,) -> AbstractMemorySystem:
def DualChannelDDR4_2400(
size: Optional[str] = None,
) -> AbstractMemorySystem:
"""
A dual channel memory system using DDR4_2400_8x8 based DIMM
"""
@@ -61,7 +67,9 @@ def DualChannelLPDDR3_1600(
return ChanneledMemory(LPDDR3_1600_1x32, 2, 64, size=size)
def HBM2Stack(size: Optional[str] = None,) -> AbstractMemorySystem:
def HBM2Stack(
size: Optional[str] = None,
) -> AbstractMemorySystem:
if not size:
size = "4GiB"
return ChanneledMemory(HBM_1000_4H_1x64, 16, 64, size=size)

4
src/python/gem5/components/memory/single_channel.py
View File

@@ -68,7 +68,9 @@ def SingleChannelLPDDR3_1600(
return ChanneledMemory(LPDDR3_1600_1x32, 1, 64, size=size)
def SingleChannelHBM(size: Optional[str] = None,) -> AbstractMemorySystem:
def SingleChannelHBM(
size: Optional[str] = None,
) -> AbstractMemorySystem:
if not size:
size = "256MiB"
return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size)

4
src/python/gem5/components/processors/simple_switchable_processor.py
View File

@@ -52,9 +52,9 @@ class SimpleSwitchableProcessor(SwitchableProcessor):
isa: Optional[ISA] = None,
) -> None:
"""
param starting_core_type: The CPU type for each type in the processor
:param starting_core_type: The CPU type for each type in the processor
to start with (i.e., when the simulation has just started).
:
:param switch_core_types: The CPU type for each core, to be switched
to..

2
src/python/m5/params.py
View File

@@ -594,7 +594,7 @@ class CheckedIntType(MetaParamValue):
)
if cls.unsigned:
cls.min = 0
cls.max = 2 ** cls.size - 1
cls.max = 2**cls.size - 1
else:
cls.min = -(2 ** (cls.size - 1))
cls.max = (2 ** (cls.size - 1)) - 1

2
src/python/m5/simulate.py
View File

@@ -58,7 +58,7 @@ from .util import fatal
from .util import attrdict
# define a MaxTick parameter, unsigned 64 bit
MaxTick = 2 ** 64 - 1
MaxTick = 2**64 - 1
_drain_manager = _m5.drain.DrainManager.instance()

1
src/python/m5/util/terminal.py
View File

@@ -80,7 +80,6 @@ try:
else:
return ""
except:
cap_string = null_cap_string

2
src/sim/RedirectPath.py
View File

@@ -30,7 +30,7 @@ from m5.proxy import *
class RedirectPath(SimObject):
""" Stores paths for filesystem redirection during syscalls. If a path
"""Stores paths for filesystem redirection during syscalls. If a path
matches 'appPath', then the syscall is redirected to the first 'hostPath'
that contains the non-overlapping portion of the path as a valid file. If
there are no hits, then the syscall is redirected to the first value.

6
src/sim/drain.hh
View File

@@ -118,11 +118,11 @@ class DrainManager
/**
* Run state fixups before a checkpoint restore operation.
*
* This is called before restoring the checkpoint and to make
* This is called before restoring the checkpoint and to make
* sure that everything has been set to drained.
*
* When restoring from a checkpoint, this function should be called
* first before calling the resume() function. And also before
* When restoring from a checkpoint, this function should be called
* first before calling the resume() function. And also before
* calling loadstate() on any object.
*
* The drain state of an object isn't stored in a checkpoint since

2
src/sst/sst_responder_interface.cc
View File

@@ -33,4 +33,4 @@ SSTResponderInterface::SSTResponderInterface()
{
}
}; // namespace gem5
}; // namespace gem5

2
src/sst/sst_responder_interface.hh
View File

@@ -66,4 +66,4 @@ class SSTResponderInterface
} // namespace gem5
#endif // __SST_RESPONDER_INTERFACE_HH__
#endif // __SST_RESPONDER_INTERFACE_HH__

2
src/systemc/dt/int/sc_nbcommon.inc
View File

@@ -2575,7 +2575,7 @@ void
CLASS_TYPE::dump(::std::ostream &os) const
{
// Save the current setting, and set the base to decimal.
::std::ios::fmtflags old_flags =
::std::ios::fmtflags old_flags =
os.setf(::std::ios::dec, ::std::ios::basefield);
os << "width = " << length() << ::std::endl;

48
src/systemc/dt/int/sc_nbfriends.inc
View File

@@ -53,7 +53,7 @@
// ----------------------------------------------------------------------------
// Naming conventions:
// For sc_signed or sc_unsigned number u:
// us : u's sign, unb : u's number of bits,
// us : u's sign, unb : u's number of bits,
// und : u's number of digits, ud : u's digits array.
// ----------------------------------------------------------------------------
@@ -63,7 +63,7 @@
// Handles cases 3 and 4 and returns the result.
CLASS_TYPE
ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
small_type vs, int vnb, int vnd, const sc_digit *vd)
{
und = vec_skip_leading_zeros(und, ud);
@@ -78,7 +78,7 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
#else
sc_digit *d = new sc_digit[nd];
#endif
d[nd - 1] = d[nd - 2] = 0;
// case 3
@@ -98,14 +98,14 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
} else {
// case 4
int cmp_res = vec_cmp(und, ud, vnd, vd);
if (cmp_res == 0) { // u == v
#ifndef SC_MAX_NBITS
delete[] d;
#endif
return CLASS_TYPE();
}
if (cmp_res > 0) { // u > v
if ((und == 1) && (vnd == 1))
d[0] = (*ud) - (*vd);
@@ -128,8 +128,8 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the case 4 and returns the result.
CLASS_TYPE
MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
CLASS_TYPE
MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
int vnb, int vnd, const sc_digit *vd)
{
und = vec_skip_leading_zeros(und, ud);
@@ -137,7 +137,7 @@ MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
int nb = unb + vnb;
int nd = und + vnd;
#ifdef SC_MAX_NBITS
test_bound(nb);
sc_digit d[MAX_NDIGITS];
@@ -146,7 +146,7 @@ MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
#endif
vec_zero(nd, d);
sc_digit ud0 = (*ud);
sc_digit vd0 = (*vd);
@@ -154,7 +154,7 @@ MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
vec_copy(und, d, ud);
} else if ((und == 1) && (ud0 == 1)) {
vec_copy(vnd, d, vd);
} else if ((und == 1) && (vnd == 1) &&
} else if ((und == 1) && (vnd == 1) &&
(ud0 < HALF_DIGIT_RADIX) && (vd0 < HALF_DIGIT_RADIX)) {
d[0] = ud0 * vd0;
} else if ((und == 1) && (ud0 < HALF_DIGIT_RADIX)) {
@@ -175,8 +175,8 @@ MUL_HELPER(small_type s, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the cases 3-4 and returns the result.
CLASS_TYPE
DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
CLASS_TYPE
DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
int vnb, int vnd, const sc_digit *vd)
{
und = vec_skip_leading_zeros(und, ud);
@@ -185,7 +185,7 @@ DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
int cmp_res = vec_cmp(und, ud, vnd, vd);
// u < v => u / v = 0 - case 4
if (cmp_res < 0)
if (cmp_res < 0)
return CLASS_TYPE();
// One extra digit for d is allocated to simplify vec_div_*().
@@ -223,8 +223,8 @@ DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the cases 3-4 and returns the result.
CLASS_TYPE
MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
CLASS_TYPE
MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
int vnb, int vnd, const sc_digit *vd)
{
und = vec_skip_leading_zeros(und, ud);
@@ -232,7 +232,7 @@ MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
int cmp_res = vec_cmp(und, ud, vnd, vd);
// u = v => u % v = 0 - case 3
if (cmp_res == 0)
if (cmp_res == 0)
return CLASS_TYPE();
sc_digit vd0 = (*vd);
@@ -280,8 +280,8 @@ MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the cases 2-5 and returns the result.
CLASS_TYPE
AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
CLASS_TYPE
AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
small_type vs, int vnb, int vnd, const sc_digit *vd)
{
int nb = sc_max(unb, vnb);
@@ -327,7 +327,7 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
if (xs > 0) { // case 2
while (y < yend)
(*d++) = (*x++) & (*y++);
while (x++ < xend)
while (x++ < xend)
(*d++) = 0;
} else { // case 3
sc_digit xcarry = 1;
@@ -372,7 +372,7 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
}
}
s = convert_signed_2C_to_SM(nb, nd, dbegin);
return CLASS_TYPE(s, nb, nd, dbegin);
return CLASS_TYPE(s, nb, nd, dbegin);
}
@@ -381,8 +381,8 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the cases 3-5 and returns the result.
CLASS_TYPE
OR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
CLASS_TYPE
OR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
small_type vs, int vnb, int vnd, const sc_digit *vd)
{
int nb = sc_max(unb, vnb);
@@ -483,8 +483,8 @@ OR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
// ----------------------------------------------------------------------------
// Handles the cases 3-5 and returns the result.
CLASS_TYPE
XOR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
CLASS_TYPE
XOR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
small_type vs, int vnb, int vnd, const sc_digit *vd)
{
int nb = sc_max(unb, vnb);

6
src/systemc/dt/int/sc_signed_bitref.inc
View File

@@ -121,8 +121,8 @@ sc_signed_bitref::operator ^= (bool b)
// #### OPTIMIZE
void
sc_signed_bitref::concat_set(int64 src, int low_i)
{
sc_signed_bitref::concat_set(int64 src, int low_i)
{
bool value = 1 & ((low_i < 64) ? (src >> low_i) : (src >> 63));
m_obj_p->set(low_i, value);
}
@@ -134,7 +134,7 @@ sc_signed_bitref::concat_set(const sc_signed &src, int low_i)
m_obj_p->set(low_i, src.test(low_i));
else
m_obj_p->set(low_i, src < 0);
}
}
void
sc_signed_bitref::concat_set(const sc_unsigned &src, int low_i)

6
src/systemc/dt/int/sc_unsigned_bitref.inc
View File

@@ -19,10 +19,10 @@
/*****************************************************************************
sc_unsigned_bitref.h -- Proxy class that is declared in sc_unsigned.h.
sc_unsigned_bitref.h -- Proxy class that is declared in sc_unsigned.h.
Original Author: Ali Dasdan, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
@@ -138,7 +138,7 @@ sc_unsigned_bitref::concat_set(const sc_signed &src, int low_i)
void
sc_unsigned_bitref::concat_set(const sc_unsigned &src, int low_i)
{
{
if (low_i < src.nbits)
m_obj_p->set(low_i, src.test(low_i));
else