misc: Remove lingering uses of TheISA::.

Change-Id: Ie55e0d79867fbc8f75a993fb456a58c84de5def4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62196
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/amdgpu/common/tlb_coalescer.cc

@@ -194,7 +194,7 @@ TLBCoalescer::updatePhysAddresses(PacketPtr pkt)
             // the correct TLBEentry in the TLBs above.
             auto p = sender_state->tc->getProcessPtr();
             sender_state->tlbEntry =
-                new TheISA::TlbEntry(p->pid(), first_entry_vaddr,
+                new X86ISA::TlbEntry(p->pid(), first_entry_vaddr,
                     first_entry_paddr, false, false);
 
             // update the hitLevel for all uncoalesced reqs

src/arch/arm/isa/includes.isa

@@ -70,6 +70,11 @@ output header {{
 #include "mem/packet.hh"
 #include "sim/faults.hh"
 
+namespace gem5::ArmISA
+{
+class Decoder;
+} // namespace gem5::ArmISA
+
 namespace gem5::ArmISAInst
 {
 using namespace ArmISA;

src/arch/mips/idle_event.cc

@@ -28,13 +28,9 @@
 
 #include "arch/mips/idle_event.hh"
 
-#include "cpu/thread_context.hh"
-
 namespace gem5
 {
 
-using namespace MipsISA;
-
 void
 IdleStartEvent::process(ThreadContext *tc)
 {

src/cpu/checker/thread_context.hh

@@ -52,11 +52,6 @@
 namespace gem5
 {
 
-namespace TheISA
-{
-    class Decoder;
-} // namespace TheISA
-
 /**
  * Derived ThreadContext class for use with the Checker.  The template
  * parameter is the ThreadContext class used by the specific CPU being

src/cpu/thread_context.hh

@@ -58,10 +58,6 @@ namespace gem5
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
-namespace TheISA
-{
-    class Decoder;
-}
 class BaseCPU;
 class BaseMMU;
 class BaseTLB;

src/dev/riscv/plic_device.cc

@@ -40,8 +40,6 @@
 namespace gem5
 {
 
-using namespace RiscvISA;
-
 PlicIntDevice::PlicIntDevice(const Params &params) :
     BasicPioDevice(params, params.pio_size),
     system(params.system),

src/dev/riscv/plic_device.hh

@@ -46,8 +46,6 @@
 namespace gem5
 {
 
-using namespace RiscvISA;
-
 class PlicIntDevice : public BasicPioDevice
 {
   protected:

src/gpu-compute/gpu_compute_driver.cc

@@ -733,13 +733,13 @@ GPUComputeDriver::ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf)
             args.copyIn(virt_proxy);
 
             assert(isdGPU || gfxVersion == GfxVersion::gfx902);
-            assert((args->va_addr % TheISA::PageBytes) == 0);
+            assert((args->va_addr % X86ISA::PageBytes) == 0);
             [[maybe_unused]] Addr mmap_offset = 0;
 
             Request::CacheCoherenceFlags mtype = defaultMtype;
             Addr pa_addr = 0;
 
-            int npages = divCeil(args->size, (int64_t)TheISA::PageBytes);
+            int npages = divCeil(args->size, (int64_t)X86ISA::PageBytes);
             bool cacheable = true;
 
             if (KFD_IOC_ALLOC_MEM_FLAGS_VRAM & args->flags) {