stdlib: Fix default values in classic caches

By default, caches in classic memory system are assume to be a mostly
inclusive cache with respect to their upstream caches.
Therefore, `writeback_clean` should be `False` by default, which is
consistent with src/mem/cache/Cache.py

Change-Id: I1395690f7f5fafee7fb151906302877ada953861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py

@@ -34,6 +34,9 @@ from typing import Type
 class L1DCache(Cache):
     """
     A simple L1 data cache with default values.
+
+    If the cache has a mostly exclusive downstream cache, writeback_clean
+    should be set to True.
     """
 
     def __init__(
@@ -45,7 +48,7 @@ class L1DCache(Cache):
         response_latency: int = 1,
         mshrs: int = 16,
         tgts_per_mshr: int = 20,
-        writeback_clean: bool = True,
+        writeback_clean: bool = False,
         PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
     ):
         super().__init__()

src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py

@@ -34,6 +34,9 @@ from .....utils.override import *
 class L1ICache(Cache):
     """
     A simple L1 instruction cache with default values.
+
+    If the cache does not have a downstream cache or the downstream cache
+    is mostly inclusive as usual, writeback_clean should be set to False.
     """
 
     def __init__(

src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py

@@ -26,7 +26,7 @@
 
 from .....utils.override import *
 
-from m5.objects import Cache, BasePrefetcher, StridePrefetcher
+from m5.objects import Cache, Clusivity, BasePrefetcher, StridePrefetcher
 
 from typing import Type
 
@@ -45,7 +45,8 @@ class L2Cache(Cache):
         response_latency: int = 1,
         mshrs: int = 20,
         tgts_per_mshr: int = 12,
-        writeback_clean: bool = True,
+        writeback_clean: bool = False,
+        clusivity: Clusivity = "mostly_incl",
         PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
     ):
         super().__init__()
@@ -57,4 +58,5 @@ class L2Cache(Cache):
         self.mshrs = mshrs
         self.tgts_per_mshr = tgts_per_mshr
         self.writeback_clean = writeback_clean
+        self.clusivity = clusivity
         self.prefetcher = PrefetcherCls()

src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py

@@ -32,6 +32,9 @@ from m5.objects import Cache, BasePrefetcher, StridePrefetcher
 class MMUCache(Cache):
     """
     A simple Memory Management Unit (MMU) cache with default values.
+
+    If the cache does not have a downstream cache or the downstream cache
+    is mostly inclusive as usual, writeback_clean should be set to False.
     """
 
     def __init__(