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5297 Commits

Author SHA1 Message Date
Giacomo Travaglini
167cf86375 arch-arm: Move access permission bitset within MiscRegLUTEntry 
Rather than having two separate MiscReg metadata vectors, we are
storing the access permission bitset within the MiscRegLUTEntry

Change-Id: I2f5d175617c888f0eb6954d29a4c607e0cbc3611
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61674
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-28 13:24:02 +00:00
Giacomo Travaglini
f118b5755a arch-arm: Move lookUpMiscReg vector out of the ISA class 
Our plan is to consolidate the lookUpMiscReg vector with the
miscRegInfo one into a single metadata vector

Change-Id: I07b5a63a8da6d9b48593a904f6912b84a2afdd2c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61673
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-07-28 13:24:02 +00:00
Giacomo Travaglini
e4ab0bb5cf arch-arm: Add a getter for miscRead member variable 
In this way our ISA code can check if a MiscRegOp64 is a MSR or a MRS
and act accordingly

Change-Id: I9ddb9df432b28ce7d20235fc51f3637c41f3256a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61672
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2022-07-28 13:24:02 +00:00
Giacomo Travaglini
07b6f4261c arch-arm: Add undefined helper to ArmStaticInst 
In this way we can generate an Undefined Instruction fault
from the instruction object without requiring to access its
menmonic or opcode

This is generalizing the existing disabledFault helper

Change-Id: Ib7dec9399f142c35d75057f37ab53cce102fa01e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61671
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2022-07-28 13:24:02 +00:00
Giacomo Travaglini
25bdb73b9f arch-arm: Generate MSR/MRS iss within trapping logic 
The iss field is only used when the MSR/MRS instruction
gets trapped. Rather than generating it at decode time,
we generate the value within the trap method instead

This avoids the confusion of having a MSR/MRS register
instruction storing an immediate field

Later patches will change this even further by generating the
iss field on the fly ONLY if the instruction gets trapped

Change-Id: I97fdcf54d9643ea79a1f9d052073320ee68109fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61670
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2022-07-28 13:24:02 +00:00
Giacomo Travaglini
6217ac737b arch-arm: Overload decodeAArch64SysReg to accept a MiscRegNum64 
Overload decodeAArch64SysReg to directly accept a MiscRegNum64

Change-Id: I43c1dae6c0e382c03612f4ce4fc89aadddf30fd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61669
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-28 13:24:02 +00:00
Gabe Black
654451c2be arch,cpu: Keep a RegClass pointer in RegId instead of a RegClassType. 
This makes it easy to get access to the RegClass that goes with a
register without having to look it up in a separate structure.

Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49786
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-27 13:54:32 +00:00
Gabe Black
45cf2e3c34 arch: Minimize use of RegClassType constants and the RegId constructor. 
These are global values which prevent making register types ISA
specific.

Change-Id: I513adcae5ad316122c24f25a9e01b9974629510f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49785
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-27 10:59:07 +00:00
Gabe Black
70289e72cd arch,cpu: Store pointers to RegClass-es instead of instances. 
This lets us put the actual RegClass-es somewhere else and give them
names.

Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49784
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
 2022-07-26 19:37:59 +00:00
Eliot Moss
23b2561bf6 cpu: x86: add serialize and fence instructions to the isa 
Clarify commented out lines.

Issue-On: https://gem5.atlassian.net/browse/GEM5-1231

Change-Id: I15d685ca233b56e0aece312bc85a9bff0d56e4dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60929
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-07-23 13:25:49 +00:00
Jui-Min Lee
f5e03741c7 arch-riscv: Make WFI halt the hart 
First, this CL modifies the implementation of WFI so it actually put the
calling CPU into sleep.

This CL also adds an id in the IRQ table to represent NMI. This is
because the wakeup path is only implemented on cpu's postInterrupt
function, and it expects an int_num.

We still keep the MISCREG for nmie and nmip instead of merging them into
other ip/ie as that will give the user ability to get/set the nmi
status, which is pretty dangerous.

Change-Id: Idf8a5748990efa20aa9372efa97d3bed2aac82d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-21 06:40:59 +00:00
Matthew Poremba
af9ecf7920 arch-vega,arch-gcn3: Add support for VCC_HI as scalar source 
Currently there is only support for VCC_LO as a scalar source. Add
support for VCC_HI as well. The op selector symbol is also changed to be
vcc_hi/vcc_lo as it is in disassembly from LLVM.

Change-Id: I19ea8e23873049c33ffe2eb4ec8504a18f371c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61329
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-18 17:27:50 +00:00
Matthew Poremba
3a73aa3ac1 arch-vega: Implement new VOP2 using VOP3 insts 
Vega adds three new VOP2 instructions that may use VOP3 encoding that
are not part of the GCN3 ISA: v_add_u32, v_sub_u32, v_subrev_u32. This
changeset implements those three new instructions to fix errors related
to "invalid encoding" when those instructions are seen.

Tested using srad from Rodinia 3.0 HIP port which compiles a v_add_u32
instruction with VOP3 encoding.

Change-Id: I409a9f72f5c37895c3a0ab7ceb14a4dd121874a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61330
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
 2022-07-15 14:55:33 +00:00
Matthew Poremba
40077055cf arch-vega: Fix disassembly for two dword VOPC 
Calling opSelectorToRegSym in the disassembly for VOPC when there is a
second dword (SDWA, DPP, or Literal) causes a panic as those registers
do not have a string symbol. This is fixed by checking for a second
dword before printing similar to how VOP1, VOP2, SOP1, etc. function.

Change-Id: I97b33e1e45abcf3ff1d0bc5754773b4eee961a98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61269
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-12 19:05:32 +00:00
ksco
f5d15871f3 arch-riscv: Treat InvalidRegClass as zero register. 
Currently the disassembler will print the zero register as ft0, this commit provides a workaround to solve this problem.

Change-Id: Ic8ac3f277dd9ff886dc84a83c022954ad30c47f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61150
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-08 00:09:01 +00:00
ksco
a4a2170409 arch-riscv: Use more precise mnemonics 
Change-Id: I520ff63b8ca88e0dab75c03a07f17430fc160ea9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61149
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-07-08 00:08:43 +00:00
ksco
8fb2dfaa6a arch-riscv: Add K extension 
This commit adds part of RISC-V Cryptography Extensions v1.0.1 to gem5. Include the following instructions:

Zbkx:
xperm8: Crossbar permutation (bytes)
xperm4: Crossbar permutation (nibbles)

Zknd:
aes64ds:   AES decrypt final round (RV64)
aes64dsm:  AES decrypt middle round (RV64)
aes64im:   AES Decrypt KeySchedule MixColumns (RV64)
aes64ks1i: AES Key Schedule Instruction 1 (RV64)
aes64ks2:  AES Key Schedule Instruction 2 (RV64)

Zkne:
aes64es:   AES encrypt final round instruction (RV64)
aes64esm:  AES encrypt middle round instruction (RV64)
aes64ks1i: AES Key Schedule Instruction 1 (RV64)
aes64ks2:  AES Key Schedule Instruction 2 (RV64)

Zknh:
sha256sig0: SHA2-256 Sigma0 instruction
sha256sig1: SHA2-256 Sigma1 instruction
sha256sum0: SHA2-256 Sum0 instruction
sha256sum1: SHA2-256 Sum1 instruction
sha512sig0: SHA2-512 Sigma0 instruction (RV64)
sha512sig1: SHA2-512 Sigma1 instruction (RV64)
sha512sum0: SHA2-512 Sum0 instruction (RV64)
sha512sum1: SHA2-512 Sum1 instruction (RV64)

Zksed:
sm4ed: SM4 Encrypt/Decrypt Instruction
sm4ks: SM4 Key Schedule Instruction

Zksh:
sm3p0: SM3 P0 transform
sm3p1: SM3 P1 transform

Change-Id: Ide3e6a4ce903be09dfb3e6b702c9dbcf74a35afb
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60949
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-07-08 00:08:01 +00:00
Giacomo Travaglini
ccdec1b11d arch-arm: Do not trap SIMD insts to EL1 if in VHE host 
Change-Id: I4ea326eead1aec1e013280b599c57f2202901625
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60971
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-05 08:45:01 +00:00
Giacomo Travaglini
343f7b7bf6 arch-arm: Do not trap MISCREG_DC_ZVA_Xt to EL1 if in VHE host 
Change-Id: I785be01fcb97b78e0b59f8f9a4f8d150208fa88a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60970
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-05 08:45:01 +00:00
Giacomo Travaglini
ea9620922c arch-arm: Revamp of AArch64 S1 access permission logic 
This patch is revamping/simplifying the access permission logic in the
ArmMMU (ArmMMU::s1PermBits64) by matching more closely the Arm
architecture reference manual pseudocode.

It also fixes VHE access permission: previous version was not
considering the EL2&0 translation regime.
Now EL2&0 is handled correctly through the new hasUnprivRegime method

Change-Id: I2689738f36a35c35cc4f2ef8af68ee2a3eef65e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60969
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-05 08:45:01 +00:00
Yu-hsin Wang
c1b709e46d fastmodel: handling amba control signals 
Change-Id: I7a62bdd4bfdb2bba4f7e186b049491b48782d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-07-04 02:59:58 +00:00
Giacomo Travaglini
b0eaecc77b arch-arm: Check if VectorCatch is nullptr 
This is needed after [1].
Simulation starts with a call to the reset fault in the
initState stage and therefore checks for the vector catch
object. This happens before the SelfDebug object is properly
initialized.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/60730

Change-Id: Ic117413611aa30386327bbc13e5489fab32733de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60769
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-27 23:35:49 +00:00
Giacomo Travaglini
b9186e2e70 arch-arm: Initialize Debug using AArch64 version of the registers 
Initialize Arm Self Hosted Debug using the AArch64 version of
Watchpoint registers

Change-Id: I2fc711970c7805d8de985846025b8f6de99b2682
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60731
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-06-24 14:03:16 +00:00
Giacomo Travaglini
58f448743b arch-arm: Remove unnecessary self hosted debug initialization 
The init method is already called by in the ISA::init, before
simulation starts, so there is no need to check for it
when a watchpoint/breakpoint is set by guest software

Change-Id: I776a1824799a7f4a351eb7d3c7002a11726f9d6a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60730
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-06-24 14:03:16 +00:00
Giacomo Travaglini
424643e91e arch-arm: Fix format specifier in encodeAArch64SysReg panic 
The panic was using the wrong format specifier: %n instead of %d

Change-Id: I92f0be85dc24da06373cba5c20bab6de7d7b4537
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60729
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-06-24 14:03:16 +00:00
Gabe Black
85a18e22a1 arch,cpu: Keep track of the RegClassType of a RegClass. 
This makes it possible to do more things with a RegClass locally.

Change-Id: Ib7d7fa3e2d88a34d5b5681fcc4aab26696c71205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49779
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-24 11:27:23 +00:00
Matt Sinclair
590719a383 arch-vega: explain when op encoder ignores src reg 
Previously b40b361bee added support for the Vega operand encoder.  As
part of this, it made sure to check for the S_GETPC_B64 instruction,
which appears to be the only instruction in the Vega ISA that does not
use the source register.  However, at the time the commit used magic
numbers without comment, which can be difficult for users to interpret.

To resolve this, this commit adds a comment to explain where the magic
numbers come from (Table 58 in the Vega ISA manual).

Change-Id: Ic5007b510e0175558d21ede8eb6db273113187b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60650
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
 2022-06-22 17:14:35 +00:00
Matt Sinclair
00008b725c arch-vega: some Vega instructions don't use dest reg 
Some of the Vega scalar instructions (S_SETPC_B64, S_RFE_B64,
S_CBRANCH_JOIN, and S_SET_GPR_IDX_IDX) do not use the SDST scalar
destination register.  However, Vega's operand encoding function for the
SOP1 instruction type's class assumed all instructions used the
destination register, which results in an assert failure for these
instructions.

To resolve this, this commit updates the Vega SOP1 operand encoder to
ignore the destination register for these specific instructions.

Change-Id: I2f0d830f6264fc7f47c0694a2fd5da5d33d2ea0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60649
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
 2022-06-22 17:14:35 +00:00
Michael Boyer
81058189af arch-vega,arch-gcn3: Implement S_MEMTIME instruction 
Change-Id: I3e286eb6ff8af4097ad03d4066be79f73d938cea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53603
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-21 20:19:46 +00:00
Gabe Black
e57205f539 arch-riscv: Revamp float regs. 
Change-Id: I6bb7a4f78e59082c3f783a5d4c2cb79f9c6df61f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49773
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-20 04:04:05 +00:00
Gabe Black
0fa9bc0780 arch-riscv: Revamp int regs. 
Change-Id: Ie4773178843757acede4fe9e77ca327f7b024270
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49772
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-20 04:03:52 +00:00
Gabe Black
6a73a3a2d0 arch: Switch the generic register ABI over to use RegId. 
Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49774
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-19 07:48:14 +00:00
Gabe Black
644ab97727 arch-sparc: Revamp the float registers. 
Change-Id: Iec52e15f1529319345795496a82a37e1f0aeebae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49769
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-19 07:21:37 +00:00
Gabe Black
0de5b1f173 arch-sparc: Revamp the int regs. 
Change-Id: Ifa968e42e55f78cea9eb92e9fc6fc906e0784594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49768
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:21:14 +00:00
Gabe Black
a0e278863f arch-sparc: Remove unused fixed register operands. 
These had been used to manually feed arguments to pseudoInsts (I think)
which is now handled automatically. Regardless, these are not used and
can be eliminated.

Change-Id: I1aeeb00627bbbfaaf550c878ee88b0b2f7f6b61d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49807
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:21:00 +00:00
Gabe Black
93fa99041d arch-mips: Convert float, int, and misc regs. 
Convert them to use namespaces, style guide compliant names, and (except
for misc regs) the new accessors.

Change-Id: I6f190658447d40b9933e498ce766ac6c629b6cbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49761
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:20:34 +00:00
Yu-hsin Wang
72290f00fd systemc: align the style in sc_ext 
Change-Id: I0a45ad9d9e3a2603878ee9bcdc1d416bb241deeb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59650
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-17 07:08:16 +00:00
Charles Jamieson
7170c365be arch-vega: implement S_GETREG_B32 instruction 
This commit adds support for the Vega GPU ISA's S_GETREG_B32
instruction.

This work was done by Charles Jamieson but I am committing.

Change-Id: Ic2e24f667ed1aec7b8b1404a06e17e7ffb192fba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60589
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-17 02:24:05 +00:00
Gabe Black
0d18112f0f arch-power: Revamp float regs. 
Change-Id: I77a5a021da82c8528d092f7363a927dec224d5ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49771
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 20:35:16 +00:00
Gabe Black
23087f124a arch-power: Revamp int registers. 
Change-Id: I2e11601a6bf37d6ca161d0ce99d7bfff1ee2f0eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49770
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-08 20:35:01 +00:00
Gabe Black
112f4104b9 arch-arm: Fix up code related to the float reg file? 
ARM no longer uses it's primitive FloatRegClass register file, but the
code in tarmac_record.cc still seems to access it? Should this code be
deleted, or rewritten to use the vector register file?

This code was used in the 32 bit ARM KVM code as well.

Change-Id: I6ed2ed9ae853fa4313294fdde4ce08d134fc12da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49767
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:34:38 +00:00
Gabe Black
7f61db0f2e arch-arm: Switch from (set|read)Vec* to (get|set)Reg* accessors. 
Change-Id: I9e9b51b965402b3c8c94cce1593d62aa2118cd0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49766
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 20:34:19 +00:00
Gabe Black
8f180369fd arch-arm: Rework the condition code regs. 
Change-Id: I0cfaaecb4da27cecc3dc6464b094fe2cf03b407a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49765
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:34:01 +00:00
Gabe Black
5efe4d4a3a arch-arm: Rework the int regs. 
Change-Id: I352e12d4742f0771859bdbf9634ac87e2c153427
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:33:42 +00:00
Gabe Black
7e6fd8423e arch-x86: Rework float regs for getReg and setReg. 
Change-Id: I9ef7493225678923964721bf91f2fd2c43d4d1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49760
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:32 +00:00
Gabe Black
d40bedc019 arch-x86: Rework CCRegs for getReg, setReg. 
Put them in a namespace, make them match the style guide, turn them into
RegIds, and replace readCCReg and setCCReg with getReg and setReg.

Change-Id: I46f766a544696caf3dcfc6b34b50f02b86766da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49759
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:09:18 +00:00
Gabe Black
84ae0afa59 arch-x86: Put misc reg indexes into a name space. 
Also make them match the style guide.

Change-Id: I845f141f85d4499a5acf56c2161240764906a232
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49758
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:05 +00:00
Gabe Black
c4ea43f462 arch-x86: De-indent arch/x86/regs/misc.hh. 
Namespaces are not supposed to increase indentation.

Change-Id: I6736c5049ea8d853dc67f319192b9eaa97d27cb1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49757
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:50 +00:00
Gabe Black
88143c940b arch-x86: Convert segment indices to fit the style guide. 
Capitalize only their first letter, and use a namespace to namespace
them instead of a SEGMENT_REG_ prefix.

Change-Id: I69778c8d052ad6cc0ffd9e74dd1c643e9d28048d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49756
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:08:37 +00:00
Gabe Black
b836e6a495 arch-x86: Stop using (read|set)IntReg. 
These accessors just translate a RegIndex x into a RegId(IntRegClass, x)
and then does (get|set)Reg. Instead, we can just do (get|set)Reg
directly, since all the integer register named constants are just RegIds
now.

Change-Id: I9e7551ed66a6979e83c745f2891c452ded1eff0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:23 +00:00