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arch,cpu: Store pointers to RegClass-es instead of instances.

Browse Source 
This lets us put the actual RegClass-es somewhere else and give them
names.

Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49784
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
This commit is contained in:
Gabe Black
2021-08-30 19:46:20 -07:00
parent 705351768c
commit 70289e72cd
36 changed files with 298 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/SConscript
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@@ -46,8 +46,8 @@ Import('*')
# Note: This will need reconfigured for multi-isa. E.g., if this is
# incorporated: https://gem5-review.googlesource.com/c/public/gem5/+/52491
if env['TARGET_ISA'] == 'arm':
GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc')
GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc',
'../../cpu/reg_class.cc', '../../sim/bufval.cc')
Source('decoder.cc', tags='arm isa')
Source('faults.cc', tags='arm isa')
Source('htm.cc', tags='arm isa')

40
src/arch/arm/isa.cc
View File

@@ -53,11 +53,7 @@
#include "cpu/checker/cpu.hh"
#include "cpu/reg_class.hh"
#include "debug/Arm.hh"
#include "debug/CCRegs.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/LLSC.hh"
#include "debug/MiscRegs.hh"
#include "debug/VecPredRegs.hh"
#include "debug/VecRegs.hh"
#include "dev/arm/generic_timer.hh"
@@ -74,37 +70,25 @@ namespace gem5
namespace ArmISA
{
class MiscRegClassOps : public RegClassOps
namespace
{
public:
std::string
regName(const RegId &id) const override
{
return miscRegName[id.index()];
}
} miscRegClassOps;
VecElemRegClassOps<ArmISA::VecElem> vecRegElemClassOps(NumVecElemPerVecReg);
TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
/* Not applicable to ARM */
RegClass floatRegClass(FloatRegClass, 0, debug::FloatRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, 0, debug::FloatRegs);
_regClasses.emplace_back(VecRegClass, NumVecRegs, vecRegClassOps,
debug::VecRegs, sizeof(VecRegContainer));
_regClasses.emplace_back(VecElemClass,
NumVecRegs * ArmISA::NumVecElemPerVecReg, vecRegElemClassOps,
debug::VecRegs);
_regClasses.emplace_back(VecPredRegClass, NumVecPredRegs,
vecPredRegClassOps, debug::VecPredRegs,
sizeof(VecPredRegContainer));
_regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, miscRegClassOps,
debug::MiscRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
miscRegs[MISCREG_SCTLR_RST] = 0;

4
src/arch/arm/regs/cc.hh
View File

@@ -39,6 +39,7 @@
#define __ARCH_ARM_REGS_CC_HH__
#include "cpu/reg_class.hh"
#include "debug/CCRegs.hh"
namespace gem5
{
@@ -79,6 +80,9 @@ const char * const RegName[NumRegs] = {
} // namespace cc_reg
inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
debug::CCRegs);
enum ConditionCode
{
COND_EQ = 0,

4
src/arch/arm/regs/int.hh
View File

@@ -46,6 +46,7 @@
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
#include "sim/core.hh"
namespace gem5
@@ -550,6 +551,9 @@ regInMode(OperatingMode mode, int reg)
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
static inline int
flattenIntRegModeIndex(int reg)
{

17
src/arch/arm/regs/misc.hh
View File

@@ -46,6 +46,8 @@
#include "arch/arm/regs/misc_types.hh"
#include "base/compiler.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"
namespace gem5
@@ -2287,6 +2289,21 @@ namespace ArmISA
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
"The miscRegName array and NUM_MISCREGS are inconsistent.");
class MiscRegClassOps : public RegClassOps
{
public:
std::string
regName(const RegId &id) const override
{
return miscRegName[id.index()];
}
};
static inline MiscRegClassOps miscRegClassOps;
inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
miscRegClassOps, debug::MiscRegs);
// This mask selects bits of the CPSR that actually go in the CondCodes
// integer register to allow renaming.
static const uint32_t CondCodesMask = 0xF00F0000;

15
src/arch/arm/regs/vec.hh
View File

@@ -44,6 +44,9 @@
#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "cpu/reg_class.hh"
#include "debug/VecPredRegs.hh"
#include "debug/VecRegs.hh"
namespace gem5
{
@@ -90,6 +93,18 @@ const int VECREG_UREG0 = 32;
const int PREDREG_FFR = 16;
const int PREDREG_UREG0 = 17;
static inline VecElemRegClassOps<ArmISA::VecElem>
vecRegElemClassOps(NumVecElemPerVecReg);
static inline TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
static inline TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
inline constexpr RegClass vecRegClass(VecRegClass, NumVecRegs, vecRegClassOps,
debug::VecRegs, sizeof(VecRegContainer));
inline constexpr RegClass vecElemClass(VecElemClass,
NumVecRegs * NumVecElemPerVecReg, vecRegElemClassOps, debug::VecRegs);
inline constexpr RegClass vecPredRegClass(VecPredRegClass, NumVecPredRegs,
vecPredRegClassOps, debug::VecPredRegs, sizeof(VecPredRegContainer));
} // namespace ArmISA
} // namespace gem5

2
src/arch/generic/isa.hh
View File

@@ -57,7 +57,7 @@ class ExecContext;
class BaseISA : public SimObject
{
public:
typedef std::vector<RegClass> RegClasses;
typedef std::vector<const RegClass *> RegClasses;
protected:
using SimObject::SimObject;

32
src/arch/mips/isa.cc
View File

@@ -38,10 +38,7 @@
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
#include "cpu/thread_context.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/MipsPRA.hh"
#include "debug/MiscRegs.hh"
#include "params/MipsISA.hh"
namespace gem5
@@ -97,20 +94,27 @@ ISA::miscRegNames[misc_reg::NumRegs] =
"LLFlag"
};
namespace
{
/* Not applicable to MIPS. */
constexpr RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
constexpr RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
constexpr RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
constexpr RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to MIPS. */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs, debug::MiscRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
miscRegFile.resize(misc_reg::NumRegs);
bankType.resize(misc_reg::NumRegs);

6
src/arch/mips/regs/float.hh
View File

@@ -32,6 +32,9 @@
#include <cstdint>
#include "cpu/reg_class.hh"
#include "debug/FloatRegs.hh"
namespace gem5
{
namespace MipsISA
@@ -146,6 +149,9 @@ enum FCSRFields
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
} // namespace MipsISA
} // namespace gem5

5
src/arch/mips/regs/int.hh
View File

@@ -31,6 +31,7 @@
#define __ARCH_MIPS_REGS_INT_HH__
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
namespace gem5
{
@@ -199,6 +200,10 @@ inline constexpr auto
&SyscallSuccess = A3;
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
} // namespace MipsISA
} // namespace gem5

7
src/arch/mips/regs/misc.hh
View File

@@ -30,6 +30,9 @@
#ifndef __ARCH_MIPS_REGS_MISC_HH__
#define __ARCH_MIPS_REGS_MISC_HH__
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
namespace gem5
{
namespace MipsISA
@@ -196,6 +199,10 @@ enum : RegIndex
};
} // namespace misc_reg
inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
} // namespace MipsISA
} // namespace gem5

28
src/arch/power/isa.cc
View File

@@ -41,9 +41,6 @@
#include "arch/power/regs/int.hh"
#include "arch/power/regs/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/MiscRegs.hh"
#include "params/PowerISA.hh"
namespace gem5
@@ -52,16 +49,25 @@ namespace gem5
namespace PowerISA
{
namespace
{
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
clear();
}

7
src/arch/power/regs/float.hh
View File

@@ -29,6 +29,9 @@
#ifndef __ARCH_POWER_REGS_FLOAT_HH__
#define __ARCH_POWER_REGS_FLOAT_HH__
#include "cpu/reg_class.hh"
#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -42,6 +45,10 @@ const int NumArchRegs = 32;
const int NumRegs = NumArchRegs;
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
} // namespace PowerISA
} // namespace gem5

4
src/arch/power/regs/int.hh
View File

@@ -31,6 +31,7 @@
#define __ARCH_POWER_REGS_INT_HH__
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
namespace gem5
{
@@ -139,6 +140,9 @@ inline constexpr RegId
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
// Semantically meaningful register indices
inline constexpr auto
&ReturnValueReg = int_reg::R3,

5
src/arch/power/regs/misc.hh
View File

@@ -31,6 +31,8 @@
#define __ARCH_POWER_MISCREGS_HH__
#include "base/bitunion.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -46,6 +48,9 @@ enum MiscRegIndex
const char * const miscRegName[NUM_MISCREGS] = {
};
inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
debug::MiscRegs);
BitUnion32(Cr)
SubBitUnion(cr0, 31, 28)
Bitfield<31> lt;

32
src/arch/riscv/isa.cc
View File

@@ -47,10 +47,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/LLSC.hh"
#include "debug/MiscRegs.hh"
#include "debug/RiscvMisc.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
@@ -194,19 +191,26 @@ namespace RiscvISA
[MISCREG_NMIP] = "NMIP",
}};
namespace
{
/* Not applicable to RISCV */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to RISCV */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
miscRegFile.resize(NUM_MISCREGS);
clear();

5
src/arch/riscv/regs/float.hh
View File

@@ -55,6 +55,7 @@
#include "base/bitfield.hh"
#include "cpu/reg_class.hh"
#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -201,6 +202,10 @@ const std::vector<std::string> RegNames = {
};
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
} // namespace RiscvISA
} // namespace gem5

4
src/arch/riscv/regs/int.hh
View File

@@ -50,6 +50,7 @@
#include <vector>
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
namespace gem5
{
@@ -126,6 +127,9 @@ const std::vector<std::string> RegNames = {
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
// Semantically meaningful register indices
inline constexpr auto
&ReturnAddrReg = int_reg::Ra,

5
src/arch/riscv/regs/misc.hh
View File

@@ -53,6 +53,8 @@
#include "arch/generic/vec_reg.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -200,6 +202,9 @@ enum MiscRegIndex
NUM_MISCREGS
};
inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
debug::MiscRegs);
enum CSRIndex
{
CSR_USTATUS = 0x000,

31
src/arch/sparc/isa.cc
View File

@@ -39,9 +39,6 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/MiscRegs.hh"
#include "debug/Timer.hh"
#include "params/SparcISA.hh"
@@ -68,19 +65,27 @@ buildPstateMask()
static const PSTATE PstateMask = buildPstateMask();
namespace
{
/* Not applicable for SPARC */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
/* Not applicable for SPARC */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NumMiscRegs, debug::MiscRegs);
clear();
}

7
src/arch/sparc/regs/float.hh
View File

@@ -29,6 +29,9 @@
#ifndef __ARCH_SPARC_REGS_FLOAT_HH__
#define __ARCH_SPARC_REGS_FLOAT_HH__
#include "cpu/reg_class.hh"
#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -42,6 +45,10 @@ const int NumRegs = 64;
const int NumArchRegs = NumRegs;
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
} // namespace SparcISA
} // namespace gem5

4
src/arch/sparc/regs/int.hh
View File

@@ -31,6 +31,7 @@
#include "arch/sparc/sparc_traits.hh"
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
namespace gem5
{
@@ -142,6 +143,9 @@ const int NumRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroRegs;
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
// the rest of these depend on the ABI
inline constexpr auto
&ReturnAddressReg = int_reg::I7, // post call, precall is 15

5
src/arch/sparc/regs/misc.hh
View File

@@ -31,6 +31,8 @@
#include "base/bitunion.hh"
#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -172,6 +174,9 @@ struct STS
const int NumMiscRegs = MISCREG_NUMMISCREGS;
inline constexpr RegClass miscRegClass(MiscRegClass, NumMiscRegs,
debug::MiscRegs);
} // namespace SparcISA
} // namespace gem5

33
src/arch/x86/isa.cc
View File

@@ -31,15 +31,12 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/mmu.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
#include "base/compiler.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/CCRegs.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
#include "debug/MiscRegs.hh"
#include "params/X86ISA.hh"
#include "sim/serialize.hh"
@@ -141,22 +138,28 @@ ISA::clear()
regVal[misc_reg::ApicBase] = lApicBase;
}
namespace
{
/* Not applicable to X86 */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
{
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to X86 */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs, debug::MiscRegs);
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
clear();
}

5
src/arch/x86/regs/ccr.hh
View File

@@ -39,6 +39,7 @@
#define __ARCH_X86_REGS_CCR_HH__
#include "cpu/reg_class.hh"
#include "debug/CCRegs.hh"
namespace gem5
{
@@ -66,6 +67,10 @@ inline constexpr RegId
Ezf(CCRegClass, _EzfIdx);
} // namespace cc_reg
inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
debug::CCRegs);
} // namespace X86ISA
} // namespace gem5

5
src/arch/x86/regs/float.hh
View File

@@ -40,6 +40,8 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "cpu/reg_class.hh"
#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -161,6 +163,9 @@ stack(int index, int top)
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
} // namespace X86ISA
} // namespace gem5

4
src/arch/x86/regs/int.hh
View File

@@ -42,6 +42,7 @@
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
namespace gem5
{
@@ -145,6 +146,9 @@ inline constexpr auto
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
// This needs to be large enough to miss all the other bits of an index.
inline constexpr RegIndex IntFoldBit = 1 << 6;

5
src/arch/x86/regs/misc.hh
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@@ -42,6 +42,8 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
//These get defined in some system headers (at least termbits.h). That confuses
//things here significantly.
@@ -536,6 +538,9 @@ segAttr(int index)
} // namespace misc_reg
inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
/**
* A type to describe the condition code bits of the RFLAGS register,
* plus two flags, EZF and ECF, which are only visible to microcode.

2
src/cpu/minor/dyn_inst.cc
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@@ -137,7 +137,7 @@ static void
printRegName(std::ostream &os, const RegId& reg,
const BaseISA::RegClasses &reg_classes)
{
const auto &reg_class = reg_classes.at(reg.classValue());
const auto &reg_class = *reg_classes.at(reg.classValue());
switch (reg.classValue()) {
case InvalidRegClass:
os << 'z';

10
src/cpu/minor/scoreboard.hh
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@@ -112,12 +112,12 @@ class Scoreboard : public Named
Named(name),
regClasses(reg_classes),
intRegOffset(0),
floatRegOffset(intRegOffset + reg_classes.at(IntRegClass).numRegs()),
ccRegOffset(floatRegOffset + reg_classes.at(FloatRegClass).numRegs()),
vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).numRegs()),
floatRegOffset(intRegOffset + reg_classes.at(IntRegClass)->numRegs()),
ccRegOffset(floatRegOffset + reg_classes.at(FloatRegClass)->numRegs()),
vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass)->numRegs()),
vecPredRegOffset(vecRegOffset +
reg_classes.at(VecElemClass).numRegs()),
numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass).numRegs()),
reg_classes.at(VecElemClass)->numRegs()),
numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass)->numRegs()),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, invalidFUIndex),

16
src/cpu/o3/cpu.cc
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@@ -194,19 +194,19 @@ CPU::CPU(const BaseO3CPUParams &params)
const auto &regClasses = params.isa[0]->regClasses();
assert(params.numPhysIntRegs >=
numThreads * regClasses.at(IntRegClass).numRegs());
numThreads * regClasses.at(IntRegClass)->numRegs());
assert(params.numPhysFloatRegs >=
numThreads * regClasses.at(FloatRegClass).numRegs());
numThreads * regClasses.at(FloatRegClass)->numRegs());
assert(params.numPhysVecRegs >=
numThreads * regClasses.at(VecRegClass).numRegs());
numThreads * regClasses.at(VecRegClass)->numRegs());
assert(params.numPhysVecPredRegs >=
numThreads * regClasses.at(VecPredRegClass).numRegs());
numThreads * regClasses.at(VecPredRegClass)->numRegs());
assert(params.numPhysCCRegs >=
numThreads * regClasses.at(CCRegClass).numRegs());
numThreads * regClasses.at(CCRegClass)->numRegs());
// Just make this a warning and go ahead anyway, to keep from having to
// add checks everywhere.
warn_if(regClasses.at(CCRegClass).numRegs() == 0 &&
warn_if(regClasses.at(CCRegClass)->numRegs() == 0 &&
params.numPhysCCRegs != 0,
"Non-zero number of physical CC regs specified, even though\n"
" ISA does not use them.");
@@ -226,7 +226,7 @@ CPU::CPU(const BaseO3CPUParams &params)
for (ThreadID tid = 0; tid < active_threads; tid++) {
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
for (auto &id: regClasses.at(type)) {
for (auto &id: *regClasses.at(type)) {
// Note that we can't use the rename() method because we don't
// want special treatment for the zero register at this point
PhysRegIdPtr phys_reg = freeList.getReg(type);
@@ -692,7 +692,7 @@ CPU::insertThread(ThreadID tid)
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
for (auto &id: regClasses.at(type)) {
for (auto &id: *regClasses.at(type)) {
PhysRegIdPtr phys_reg = freeList.getReg(type);
renameMap[tid].setEntry(id, phys_reg);
scoreboard.setReg(phys_reg);

4
src/cpu/o3/inst_queue.cc
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@@ -105,8 +105,8 @@ InstructionQueue::InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
numPhysRegs = params.numPhysIntRegs + params.numPhysFloatRegs +
params.numPhysVecRegs +
params.numPhysVecRegs * (
reg_classes.at(VecElemClass).numRegs() /
reg_classes.at(VecRegClass).numRegs()) +
reg_classes.at(VecElemClass)->numRegs() /
reg_classes.at(VecRegClass)->numRegs()) +
params.numPhysVecPredRegs +
params.numPhysCCRegs;

23
src/cpu/o3/regfile.cc
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@@ -55,20 +55,21 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses &reg_classes)
: intRegFile(reg_classes.at(IntRegClass), _numPhysicalIntRegs),
floatRegFile(reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
vectorRegFile(reg_classes.at(VecRegClass), _numPhysicalVecRegs),
vectorElemRegFile(reg_classes.at(VecElemClass), _numPhysicalVecRegs * (
reg_classes.at(VecElemClass).numRegs() /
reg_classes.at(VecRegClass).numRegs())),
vecPredRegFile(reg_classes.at(VecPredRegClass), _numPhysicalVecPredRegs),
ccRegFile(reg_classes.at(CCRegClass), _numPhysicalCCRegs),
: intRegFile(*reg_classes.at(IntRegClass), _numPhysicalIntRegs),
floatRegFile(*reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
vectorRegFile(*reg_classes.at(VecRegClass), _numPhysicalVecRegs),
vectorElemRegFile(*reg_classes.at(VecElemClass), _numPhysicalVecRegs * (
reg_classes.at(VecElemClass)->numRegs() /
reg_classes.at(VecRegClass)->numRegs())),
vecPredRegFile(*reg_classes.at(VecPredRegClass),
_numPhysicalVecPredRegs),
ccRegFile(*reg_classes.at(CCRegClass), _numPhysicalCCRegs),
numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalVecRegs(_numPhysicalVecRegs),
numPhysicalVecElemRegs(_numPhysicalVecRegs * (
reg_classes.at(VecElemClass).numRegs() /
reg_classes.at(VecRegClass).numRegs())),
reg_classes.at(VecElemClass)->numRegs() /
reg_classes.at(VecRegClass)->numRegs())),
numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
numPhysicalCCRegs(_numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
@@ -116,7 +117,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
}
// Misc regs have a fixed mapping but still need PhysRegIds.
for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass).numRegs();
for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass)->numRegs();
phys_reg++) {
miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
}

2
src/cpu/o3/rename_map.cc
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@@ -114,7 +114,7 @@ UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
regFile = _regFile;
for (int i = 0; i < renameMaps.size(); i++)
renameMaps[i].init(regClasses.at(i), &(freeList->freeLists[i]));
renameMaps[i].init(*regClasses.at(i), &(freeList->freeLists[i]));
}
bool

12
src/cpu/simple_thread.cc
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@@ -71,12 +71,12 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
BaseISA *_isa, InstDecoder *_decoder)
: ThreadState(_cpu, _thread_num, _process),
regFiles{{
{_isa->regClasses().at(IntRegClass)},
{_isa->regClasses().at(FloatRegClass)},
{_isa->regClasses().at(VecRegClass)},
{_isa->regClasses().at(VecElemClass)},
{_isa->regClasses().at(VecPredRegClass)},
{_isa->regClasses().at(CCRegClass)}
{*_isa->regClasses().at(IntRegClass)},
{*_isa->regClasses().at(FloatRegClass)},
{*_isa->regClasses().at(VecRegClass)},
{*_isa->regClasses().at(VecElemClass)},
{*_isa->regClasses().at(VecPredRegClass)},
{*_isa->regClasses().at(CCRegClass)}
}},
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),

72
src/cpu/thread_context.cc
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@@ -65,7 +65,7 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
DPRINTF(Context, "Comparing thread contexts\n");
// First loop through the integer registers.
for (auto &id: regClasses.at(IntRegClass)) {
for (auto &id: *regClasses.at(IntRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -74,7 +74,7 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
}
// Then loop through the floating point registers.
for (auto &id: regClasses.at(FloatRegClass)) {
for (auto &id: *regClasses.at(FloatRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -83,34 +83,34 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
}
// Then loop through the vector registers.
const auto &vec_class = regClasses.at(VecRegClass);
std::vector<uint8_t> vec1(vec_class.regBytes());
std::vector<uint8_t> vec2(vec_class.regBytes());
for (auto &id: regClasses.at(VecRegClass)) {
const auto *vec_class = regClasses.at(VecRegClass);
std::vector<uint8_t> vec1(vec_class->regBytes());
std::vector<uint8_t> vec2(vec_class->regBytes());
for (auto &id: *regClasses.at(VecRegClass)) {
one->getReg(id, vec1.data());
two->getReg(id, vec2.data());
if (vec1 != vec2) {
panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
id.index(), vec_class.valString(vec1.data()),
vec_class.valString(vec2.data()));
id.index(), vec_class->valString(vec1.data()),
vec_class->valString(vec2.data()));
}
}
// Then loop through the predicate registers.
const auto &vec_pred_class = regClasses.at(VecPredRegClass);
std::vector<uint8_t> pred1(vec_pred_class.regBytes());
std::vector<uint8_t> pred2(vec_pred_class.regBytes());
for (auto &id: regClasses.at(VecPredRegClass)) {
const auto *vec_pred_class = regClasses.at(VecPredRegClass);
std::vector<uint8_t> pred1(vec_pred_class->regBytes());
std::vector<uint8_t> pred2(vec_pred_class->regBytes());
for (auto &id: *regClasses.at(VecPredRegClass)) {
one->getReg(id, pred1.data());
two->getReg(id, pred2.data());
if (pred1 != pred2) {
panic("Pred reg idx %d doesn't match, one: %s, two: %s",
id.index(), vec_pred_class.valString(pred1.data()),
vec_pred_class.valString(pred2.data()));
id.index(), vec_pred_class->valString(pred1.data()),
vec_pred_class->valString(pred2.data()));
}
}
for (int i = 0; i < regClasses.at(MiscRegClass).numRegs(); ++i) {
for (int i = 0; i < regClasses.at(MiscRegClass)->numRegs(); ++i) {
RegVal t1 = one->readMiscRegNoEffect(i);
RegVal t2 = two->readMiscRegNoEffect(i);
if (t1 != t2)
@@ -119,7 +119,7 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
}
// loop through the Condition Code registers.
for (auto &id: regClasses.at(CCRegClass)) {
for (auto &id: *regClasses.at(CCRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -215,36 +215,36 @@ serialize(const ThreadContext &tc, CheckpointOut &cp)
auto &nc_tc = const_cast<ThreadContext &>(tc);
const auto &regClasses = nc_tc.getIsaPtr()->regClasses();
const size_t numFloats = regClasses.at(FloatRegClass).numRegs();
const size_t numFloats = regClasses.at(FloatRegClass)->numRegs();
RegVal floatRegs[numFloats];
for (auto &id: regClasses.at(FloatRegClass))
for (auto &id: *regClasses.at(FloatRegClass))
floatRegs[id.index()] = tc.getRegFlat(id);
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats);
const size_t numVecs = regClasses.at(VecRegClass).numRegs();
const size_t numVecs = regClasses.at(VecRegClass)->numRegs();
std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
for (auto &id: regClasses.at(VecRegClass))
for (auto &id: *regClasses.at(VecRegClass))
tc.getRegFlat(id, &vecRegs[id.index()]);
SERIALIZE_CONTAINER(vecRegs);
const size_t numPreds = regClasses.at(VecPredRegClass).numRegs();
const size_t numPreds = regClasses.at(VecPredRegClass)->numRegs();
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
for (auto &id: regClasses.at(VecPredRegClass))
for (auto &id: *regClasses.at(VecPredRegClass))
tc.getRegFlat(id, &vecPredRegs[id.index()]);
SERIALIZE_CONTAINER(vecPredRegs);
const size_t numInts = regClasses.at(IntRegClass).numRegs();
const size_t numInts = regClasses.at(IntRegClass)->numRegs();
RegVal intRegs[numInts];
for (auto &id: regClasses.at(IntRegClass))
for (auto &id: *regClasses.at(IntRegClass))
intRegs[id.index()] = tc.getRegFlat(id);
SERIALIZE_ARRAY(intRegs, numInts);
const size_t numCcs = regClasses.at(CCRegClass).numRegs();
const size_t numCcs = regClasses.at(CCRegClass)->numRegs();
if (numCcs) {
RegVal ccRegs[numCcs];
for (auto &id: regClasses.at(CCRegClass))
for (auto &id: *regClasses.at(CCRegClass))
ccRegs[id.index()] = tc.getRegFlat(id);
SERIALIZE_ARRAY(ccRegs, numCcs);
}
@@ -259,37 +259,37 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
{
const auto &regClasses = tc.getIsaPtr()->regClasses();
const size_t numFloats = regClasses.at(FloatRegClass).numRegs();
const size_t numFloats = regClasses.at(FloatRegClass)->numRegs();
RegVal floatRegs[numFloats];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats);
for (auto &id: regClasses.at(FloatRegClass))
for (auto &id: *regClasses.at(FloatRegClass))
tc.setRegFlat(id, floatRegs[id.index()]);
const size_t numVecs = regClasses.at(VecRegClass).numRegs();
const size_t numVecs = regClasses.at(VecRegClass)->numRegs();
std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
UNSERIALIZE_CONTAINER(vecRegs);
for (auto &id: regClasses.at(VecRegClass))
for (auto &id: *regClasses.at(VecRegClass))
tc.setRegFlat(id, &vecRegs[id.index()]);
const size_t numPreds = regClasses.at(VecPredRegClass).numRegs();
const size_t numPreds = regClasses.at(VecPredRegClass)->numRegs();
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
UNSERIALIZE_CONTAINER(vecPredRegs);
for (auto &id: regClasses.at(VecPredRegClass))
for (auto &id: *regClasses.at(VecPredRegClass))
tc.setRegFlat(id, &vecPredRegs[id.index()]);
const size_t numInts = regClasses.at(IntRegClass).numRegs();
const size_t numInts = regClasses.at(IntRegClass)->numRegs();
RegVal intRegs[numInts];
UNSERIALIZE_ARRAY(intRegs, numInts);
for (auto &id: regClasses.at(IntRegClass))
for (auto &id: *regClasses.at(IntRegClass))
tc.setRegFlat(id, intRegs[id.index()]);
const size_t numCcs = regClasses.at(CCRegClass).numRegs();
const size_t numCcs = regClasses.at(CCRegClass)->numRegs();
if (numCcs) {
RegVal ccRegs[numCcs];
UNSERIALIZE_ARRAY(ccRegs, numCcs);
for (auto &id: regClasses.at(CCRegClass))
for (auto &id: *regClasses.at(CCRegClass))
tc.setRegFlat(id, ccRegs[id.index()]);
}