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arch-arm: Move access permission bitset within MiscRegLUTEntry

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Rather than having two separate MiscReg metadata vectors, we are
storing the access permission bitset within the MiscRegLUTEntry

Change-Id: I2f5d175617c888f0eb6954d29a4c607e0cbc3611
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61674
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-06 17:01:05 +01:00
parent f118b5755a
commit 167cf86375
8 changed files with 148 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/arm/isa.cc
View File

@@ -766,8 +766,9 @@ ISA::readMiscReg(int misc_reg)
}
#ifndef NDEBUG
if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
auto& miscreg_info = lookUpMiscReg[misc_reg].info;
if (!miscreg_info[MISCREG_IMPLEMENTED]) {
if (miscreg_info[MISCREG_WARN_NOT_FAIL])
warn("Unimplemented system register %s read.\n",
miscRegName[misc_reg]);
else
@@ -1143,8 +1144,9 @@ ISA::setMiscReg(int misc_reg, RegVal val)
}
} else {
#ifndef NDEBUG
if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
auto& miscreg_info = lookUpMiscReg[misc_reg].info;
if (!miscreg_info[MISCREG_IMPLEMENTED]) {
if (miscreg_info[MISCREG_WARN_NOT_FAIL])
warn("Unimplemented system register %s write with %#x.\n",
miscRegName[misc_reg], val);
else

13
src/arch/arm/isa.hh
View File

@@ -110,8 +110,7 @@ namespace ArmISA
const MiscRegLUTEntryInitializer
InitReg(uint32_t reg)
{
return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
miscRegInfo[reg]);
return MiscRegLUTEntryInitializer(lookUpMiscReg[reg]);
}
void initializeMiscRegMetadata();
@@ -342,7 +341,7 @@ namespace ArmISA
flat_idx = MISCREG_SPSR;
break;
}
} else if (miscRegInfo[reg][MISCREG_MUTEX]) {
} else if (lookUpMiscReg[reg].info[MISCREG_MUTEX]) {
// Mutually exclusive CP15 register
switch (reg) {
case MISCREG_PRRR_MAIR0:
@@ -391,7 +390,7 @@ namespace ArmISA
break;
}
} else {
if (miscRegInfo[reg][MISCREG_BANKED]) {
if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
bool secure_reg = !highestELIs64 && inSecureState();
flat_idx += secure_reg ? 2 : 1;
} else {
@@ -412,7 +411,7 @@ namespace ArmISA
snsBankedIndex64(MiscRegIndex reg, bool ns) const
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED64]) {
if (lookUpMiscReg[reg].info[MISCREG_BANKED64]) {
reg_as_int += (release->has(ArmExtension::SECURITY) && !ns) ?
2 : 1;
}
@@ -435,8 +434,8 @@ namespace ArmISA
int lower = lookUpMiscReg[flat_idx].lower;
int upper = lookUpMiscReg[flat_idx].upper;
// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
lower += S && lookUpMiscReg[lower].info[MISCREG_BANKED_CHILD];
upper += S && lookUpMiscReg[upper].info[MISCREG_BANKED_CHILD];
return std::make_pair(lower, upper);
}

8
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -487,9 +487,9 @@ namespace Aarch64
read ? "mrs" : "msr",
machInst, MiscRegNum64(op0, op1, crn, crm, op2),
rt, read, full_mnemonic,
miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]);
lookUpMiscReg[miscReg].info[MISCREG_WARN_NOT_FAIL]);
} else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
} else if (lookUpMiscReg[miscReg].info[MISCREG_IMPLEMENTED]) {
if (miscReg == MISCREG_NZCV) {
if (read)
return new MrsNZCV64(machInst, rt, miscReg);
@@ -498,7 +498,7 @@ namespace Aarch64
}
if (read) {
StaticInstPtr si = new Mrs64(machInst, rt, miscReg);
if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
if (lookUpMiscReg[miscReg].info[MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
} else {
@@ -555,7 +555,7 @@ namespace Aarch64
return new Msr64(machInst, miscReg, rt);
}
}
} else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
} else if (lookUpMiscReg[miscReg].info[MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",
read ? "mrs" : "msr", miscRegName[miscReg]);
return new WarnUnimplemented(read ? "mrs" : "msr",

92
src/arch/arm/isa/formats/misc.isa
View File

@@ -202,34 +202,34 @@ let {{
const uint32_t crn = bits(machInst, 19, 16);
const uint32_t opc2 = bits(machInst, 7, 5);
const uint32_t crm = bits(machInst, 3, 0);
const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
const MiscRegIndex misc_reg = decodeCP15Reg(crn, opc1, crm, opc2);
const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
const bool isRead = bits(machInst, 20);
uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
const bool is_read = bits(machInst, 20);
uint32_t iss = mcrMrcIssBuild(is_read, crm, rt, crn, opc1, opc2);
switch (miscReg) {
switch (misc_reg) {
case MISCREG_NOP:
return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
return new McrMrcMiscInst(is_read ? "mrc nop" : "mcr nop",
machInst, iss, MISCREG_NOP);
case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
return new FailUnimplemented(is_read ? "mrc unkown" : "mcr unkown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
crn, opc1, crm, opc2, isRead ? "read" : "write"));
crn, opc1, crm, opc2, is_read ? "read" : "write"));
case MISCREG_IMPDEF_UNIMPL:
if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
if (lookUpMiscReg[misc_reg].info[MISCREG_WARN_NOT_FAIL]) {
auto mnemonic =
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s",
crn, opc1, crm, opc2, isRead ? "read" : "write");
crn, opc1, crm, opc2, is_read ? "read" : "write");
return new WarnUnimplemented(
isRead ? "mrc implementation defined" :
"mcr implementation defined",
is_read ? "mrc implementation defined" :
"mcr implementation defined",
machInst, mnemonic + " treated as NOP");
} else {
return new McrMrcImplDefined(
isRead ? "mrc implementation defined" :
is_read ? "mrc implementation defined" :
"mcr implementation defined",
machInst, iss, MISCREG_IMPDEF_UNIMPL);
}
@@ -240,13 +240,13 @@ let {{
case MISCREG_CP15DMB:
return new Dmb(machInst, iss);
case MISCREG_DCIMVAC:
return new McrDcimvac(machInst, miscReg, rt, iss);
return new McrDcimvac(machInst, misc_reg, rt, iss);
case MISCREG_DCCMVAC:
return new McrDccmvac(machInst, miscReg, rt, iss);
return new McrDccmvac(machInst, misc_reg, rt, iss);
case MISCREG_DCCMVAU:
return new McrDccmvau(machInst, miscReg, rt, iss);
return new McrDccmvau(machInst, misc_reg, rt, iss);
case MISCREG_DCCIMVAC:
return new McrDccimvac(machInst, miscReg, rt, iss);
return new McrDccimvac(machInst, misc_reg, rt, iss);
case MISCREG_TLBIALL:
case MISCREG_TLBIALLIS:
case MISCREG_ITLBIALL:
@@ -277,11 +277,12 @@ let {{
case MISCREG_TLBIALLNSNHIS:
case MISCREG_TLBIALLH:
case MISCREG_TLBIALLHIS:
return new Tlbi(machInst, miscReg, rt, iss);
return new Tlbi(machInst, misc_reg, rt, iss);
default:
if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
auto& miscreg_info = lookUpMiscReg[misc_reg].info;
if (miscreg_info[MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",
isRead ? "mrc" : "mcr", miscRegName[miscReg]);
is_read ? "mrc" : "mcr", miscRegName[misc_reg]);
warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
// Remove the warn flag and set the implemented flag. This
@@ -290,18 +291,18 @@ let {{
// creating the instruction to access an register that isn't
// implemented sounds a bit silly, but its required to get
// the correct behaviour for hyp traps and undef exceptions.
miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
miscreg_info[MISCREG_IMPLEMENTED] = true;
miscreg_info[MISCREG_WARN_NOT_FAIL] = false;
}
if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
if (isRead)
return new Mrc15(machInst, rt, miscReg, iss);
return new Mcr15(machInst, miscReg, rt, iss);
if (miscreg_info[MISCREG_IMPLEMENTED]) {
if (is_read)
return new Mrc15(machInst, rt, misc_reg, iss);
return new Mcr15(machInst, misc_reg, rt, iss);
} else {
return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
csprintf("%s %s", isRead ? "mrc" : "mcr",
miscRegName[miscReg]));
return new FailUnimplemented(is_read ? "mrc" : "mcr", machInst,
csprintf("%s %s", is_read ? "mrc" : "mcr",
miscRegName[misc_reg]));
}
}
}
@@ -325,21 +326,22 @@ let {{
{
const uint32_t crm = bits(machInst, 3, 0);
const uint32_t opc1 = bits(machInst, 7, 4);
const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
const MiscRegIndex misc_reg = decodeCP15Reg64(crm, opc1);
const RegIndex rt = (RegIndex) (uint32_t) bits(machInst, 15, 12);
const RegIndex rt2 = (RegIndex) (uint32_t) bits(machInst, 19, 16);
const bool isRead = bits(machInst, 20);
const bool is_read = bits(machInst, 20);
switch (miscReg) {
switch (misc_reg) {
case MISCREG_UNKNOWN:
return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
return new FailUnimplemented(is_read ? "mrc" : "mcr", machInst,
csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
crm, opc1, isRead ? "read" : "write"));
crm, opc1, is_read ? "read" : "write"));
default:
if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
auto& miscreg_info = lookUpMiscReg[misc_reg].info;
if (miscreg_info[MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",
isRead ? "mrrc" : "mcrr", miscRegName[miscReg]);
is_read ? "mrrc" : "mcrr", miscRegName[misc_reg]);
warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
// Remove the warn flag and set the implemented flag. This
@@ -348,24 +350,24 @@ let {{
// creating the instruction to access an register that isn't
// implemented sounds a bit silly, but its required to get
// the correct behaviour for hyp traps and undef exceptions.
miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
miscreg_info[MISCREG_IMPLEMENTED] = true;
miscreg_info[MISCREG_WARN_NOT_FAIL] = false;
}
if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
if (miscreg_info[MISCREG_IMPLEMENTED]) {
uint32_t iss = mcrrMrrcIssBuild(is_read, crm, rt, rt2, opc1);
if (isRead) {
StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss);
if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
if (is_read) {
StaticInstPtr si = new Mrrc15(machInst, misc_reg, rt2, rt, iss);
if (miscreg_info[MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
}
return new Mcrr15(machInst, rt2, rt, miscReg, iss);
return new Mcrr15(machInst, rt2, rt, misc_reg, iss);
} else {
return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,
return new FailUnimplemented(is_read ? "mrrc" : "mcrr", machInst,
csprintf("%s %s",
isRead ? "mrrc" : "mcrr", miscRegName[miscReg]));
is_read ? "mrrc" : "mcrr", miscRegName[misc_reg]));
}
}
}

2
src/arch/arm/isa/insts/data64.isa
View File

@@ -547,7 +547,7 @@ let {{
MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) {
if (!lookUpMiscReg[misc_index].info[MISCREG_IMPLEMENTED]) {
return std::make_shared<UndefinedInstruction>(
machInst, false,
mnemonic);

2
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -391,7 +391,7 @@ ArmV8KvmCPU::getSysRegMap() const
const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM));
const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2));
const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
const auto &info(miscRegInfo[idx]);
const auto &info(lookUpMiscReg[idx].info);
const bool writeable(
info[MISCREG_USR_NS_WR] || info[MISCREG_USR_S_WR] ||
info[MISCREG_PRI_S_WR] || info[MISCREG_PRI_NS_WR] ||

95
src/arch/arm/regs/misc.cc
View File

@@ -562,13 +562,14 @@ std::tuple<bool, bool>
canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
{
bool secure = !scr.ns;
bool canRead = false;
bool can_read = false;
bool undefined = false;
auto& miscreg_info = lookUpMiscReg[reg].info;
switch (cpsr.mode) {
case MODE_USER:
canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
can_read = secure ? miscreg_info[MISCREG_USR_S_RD] :
miscreg_info[MISCREG_USR_NS_RD];
break;
case MODE_FIQ:
case MODE_IRQ:
@@ -576,15 +577,15 @@ canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
case MODE_ABORT:
case MODE_UNDEFINED:
case MODE_SYSTEM:
canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
can_read = secure ? miscreg_info[MISCREG_PRI_S_RD] :
miscreg_info[MISCREG_PRI_NS_RD];
break;
case MODE_MON:
canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
miscRegInfo[reg][MISCREG_MON_NS1_RD];
can_read = secure ? miscreg_info[MISCREG_MON_NS0_RD] :
miscreg_info[MISCREG_MON_NS1_RD];
break;
case MODE_HYP:
canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
can_read = miscreg_info[MISCREG_HYP_NS_RD];
break;
default:
undefined = true;
@@ -600,21 +601,22 @@ canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
}
// can't do permissions checkes on the root of a banked pair of regs
assert(!miscRegInfo[reg][MISCREG_BANKED]);
return std::make_tuple(canRead, undefined);
assert(!miscreg_info[MISCREG_BANKED]);
return std::make_tuple(can_read, undefined);
}
std::tuple<bool, bool>
canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
{
bool secure = !scr.ns;
bool canWrite = false;
bool can_write = false;
bool undefined = false;
const auto& miscreg_info = lookUpMiscReg[reg].info;
switch (cpsr.mode) {
case MODE_USER:
canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
miscRegInfo[reg][MISCREG_USR_NS_WR];
can_write = secure ? miscreg_info[MISCREG_USR_S_WR] :
miscreg_info[MISCREG_USR_NS_WR];
break;
case MODE_FIQ:
case MODE_IRQ:
@@ -622,15 +624,15 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
case MODE_ABORT:
case MODE_UNDEFINED:
case MODE_SYSTEM:
canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
can_write = secure ? miscreg_info[MISCREG_PRI_S_WR] :
miscreg_info[MISCREG_PRI_NS_WR];
break;
case MODE_MON:
canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
miscRegInfo[reg][MISCREG_MON_NS1_WR];
can_write = secure ? miscreg_info[MISCREG_MON_NS0_WR] :
miscreg_info[MISCREG_MON_NS1_WR];
break;
case MODE_HYP:
canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
can_write = miscreg_info[MISCREG_HYP_NS_WR];
break;
default:
undefined = true;
@@ -646,8 +648,8 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
}
// can't do permissions checkes on the root of a banked pair of regs
assert(!miscRegInfo[reg][MISCREG_BANKED]);
return std::make_tuple(canWrite, undefined);
assert(!miscreg_info[MISCREG_BANKED]);
return std::make_tuple(can_write, undefined);
}
bool
@@ -673,7 +675,7 @@ int
snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {
if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
!ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
}
@@ -703,9 +705,9 @@ preUnflattenMiscReg()
{
int reg = -1;
for (int i = 0 ; i < NUM_MISCREGS; i++){
if (miscRegInfo[i][MISCREG_BANKED])
if (lookUpMiscReg[i].info[MISCREG_BANKED])
reg = i;
if (miscRegInfo[i][MISCREG_BANKED_CHILD])
if (lookUpMiscReg[i].info[MISCREG_BANKED_CHILD])
unflattenResultMiscReg[i] = reg;
else
unflattenResultMiscReg[i] = i;
@@ -742,26 +744,27 @@ canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
const auto& miscreg_info = lookUpMiscReg[reg].info;
switch (currEL(cpsr)) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
return secure ? miscreg_info[MISCREG_USR_S_RD] :
miscreg_info[MISCREG_USR_NS_RD];
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
return secure ? miscreg_info[MISCREG_PRI_S_RD] :
miscreg_info[MISCREG_PRI_NS_RD];
case EL2:
if (el2_host) {
return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
return secure ? miscreg_info[MISCREG_HYP_E2H_S_RD] :
miscreg_info[MISCREG_HYP_E2H_NS_RD];
} else {
return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
miscRegInfo[reg][MISCREG_HYP_NS_RD];
return secure ? miscreg_info[MISCREG_HYP_S_RD] :
miscreg_info[MISCREG_HYP_NS_RD];
}
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
miscRegInfo[reg][MISCREG_MON_NS1_RD];
return el2_host ? miscreg_info[MISCREG_MON_E2H_RD] :
secure ? miscreg_info[MISCREG_MON_NS0_RD] :
miscreg_info[MISCREG_MON_NS1_RD];
default:
panic("Invalid exception level");
}
@@ -778,33 +781,33 @@ canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
const auto& miscreg_info = lookUpMiscReg[reg].info;
switch (el) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
miscRegInfo[reg][MISCREG_USR_NS_WR];
return secure ? miscreg_info[MISCREG_USR_S_WR] :
miscreg_info[MISCREG_USR_NS_WR];
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
return secure ? miscreg_info[MISCREG_PRI_S_WR] :
miscreg_info[MISCREG_PRI_NS_WR];
case EL2:
if (el2_host) {
return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
return secure ? miscreg_info[MISCREG_HYP_E2H_S_WR] :
miscreg_info[MISCREG_HYP_E2H_NS_WR];
} else {
return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
miscRegInfo[reg][MISCREG_HYP_NS_WR];
return secure ? miscreg_info[MISCREG_HYP_S_WR] :
miscreg_info[MISCREG_HYP_NS_WR];
}
case EL3:
return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
miscRegInfo[reg][MISCREG_MON_NS1_WR];
return el2_host ? miscreg_info[MISCREG_MON_E2H_WR] :
secure ? miscreg_info[MISCREG_MON_NS0_WR] :
miscreg_info[MISCREG_MON_NS1_WR];
default:
panic("Invalid exception level");
}
}
std::vector<struct MiscRegLUTEntry> lookUpMiscReg(NUM_MISCREGS);
std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
namespace {

70
src/arch/arm/regs/misc.hh
View File

@@ -1162,10 +1162,12 @@ namespace ArmISA
uint64_t _res1; // reserved
uint64_t _raz; // read as zero (fixed at 0)
uint64_t _rao; // read as one (fixed at 1)
std::bitset<NUM_MISCREG_INFOS> info;
public:
MiscRegLUTEntry() :
lower(0), upper(0),
_reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
_reset(0), _res0(0), _res1(0), _raz(0), _rao(0), info(0)
{}
uint64_t reset() const { return _reset; }
uint64_t res0() const { return _res0; }
uint64_t res1() const { return _res1; }
@@ -1179,7 +1181,6 @@ namespace ArmISA
class MiscRegLUTEntryInitializer
{
struct MiscRegLUTEntry &entry;
std::bitset<NUM_MISCREG_INFOS> &info;
typedef const MiscRegLUTEntryInitializer& chain;
public:
chain
@@ -1216,7 +1217,7 @@ namespace ArmISA
chain
implemented(bool v = true) const
{
info[MISCREG_IMPLEMENTED] = v;
entry.info[MISCREG_IMPLEMENTED] = v;
return *this;
}
chain
@@ -1227,61 +1228,61 @@ namespace ArmISA
chain
unverifiable(bool v = true) const
{
info[MISCREG_UNVERIFIABLE] = v;
entry.info[MISCREG_UNVERIFIABLE] = v;
return *this;
}
chain
warnNotFail(bool v = true) const
{
info[MISCREG_WARN_NOT_FAIL] = v;
entry.info[MISCREG_WARN_NOT_FAIL] = v;
return *this;
}
chain
mutex(bool v = true) const
{
info[MISCREG_MUTEX] = v;
entry.info[MISCREG_MUTEX] = v;
return *this;
}
chain
banked(bool v = true) const
{
info[MISCREG_BANKED] = v;
entry.info[MISCREG_BANKED] = v;
return *this;
}
chain
banked64(bool v = true) const
{
info[MISCREG_BANKED64] = v;
entry.info[MISCREG_BANKED64] = v;
return *this;
}
chain
bankedChild(bool v = true) const
{
info[MISCREG_BANKED_CHILD] = v;
entry.info[MISCREG_BANKED_CHILD] = v;
return *this;
}
chain
userNonSecureRead(bool v = true) const
{
info[MISCREG_USR_NS_RD] = v;
entry.info[MISCREG_USR_NS_RD] = v;
return *this;
}
chain
userNonSecureWrite(bool v = true) const
{
info[MISCREG_USR_NS_WR] = v;
entry.info[MISCREG_USR_NS_WR] = v;
return *this;
}
chain
userSecureRead(bool v = true) const
{
info[MISCREG_USR_S_RD] = v;
entry.info[MISCREG_USR_S_RD] = v;
return *this;
}
chain
userSecureWrite(bool v = true) const
{
info[MISCREG_USR_S_WR] = v;
entry.info[MISCREG_USR_S_WR] = v;
return *this;
}
chain
@@ -1296,13 +1297,13 @@ namespace ArmISA
chain
privNonSecureRead(bool v = true) const
{
info[MISCREG_PRI_NS_RD] = v;
entry.info[MISCREG_PRI_NS_RD] = v;
return *this;
}
chain
privNonSecureWrite(bool v = true) const
{
info[MISCREG_PRI_NS_WR] = v;
entry.info[MISCREG_PRI_NS_WR] = v;
return *this;
}
chain
@@ -1315,13 +1316,13 @@ namespace ArmISA
chain
privSecureRead(bool v = true) const
{
info[MISCREG_PRI_S_RD] = v;
entry.info[MISCREG_PRI_S_RD] = v;
return *this;
}
chain
privSecureWrite(bool v = true) const
{
info[MISCREG_PRI_S_WR] = v;
entry.info[MISCREG_PRI_S_WR] = v;
return *this;
}
chain
@@ -1348,13 +1349,13 @@ namespace ArmISA
chain
hypE2HSecureRead(bool v = true) const
{
info[MISCREG_HYP_E2H_S_RD] = v;
entry.info[MISCREG_HYP_E2H_S_RD] = v;
return *this;
}
chain
hypE2HNonSecureRead(bool v = true) const
{
info[MISCREG_HYP_E2H_NS_RD] = v;
entry.info[MISCREG_HYP_E2H_NS_RD] = v;
return *this;
}
chain
@@ -1367,13 +1368,13 @@ namespace ArmISA
chain
hypE2HSecureWrite(bool v = true) const
{
info[MISCREG_HYP_E2H_S_WR] = v;
entry.info[MISCREG_HYP_E2H_S_WR] = v;
return *this;
}
chain
hypE2HNonSecureWrite(bool v = true) const
{
info[MISCREG_HYP_E2H_NS_WR] = v;
entry.info[MISCREG_HYP_E2H_NS_WR] = v;
return *this;
}
chain
@@ -1393,13 +1394,13 @@ namespace ArmISA
chain
hypSecureRead(bool v = true) const
{
info[MISCREG_HYP_S_RD] = v;
entry.info[MISCREG_HYP_S_RD] = v;
return *this;
}
chain
hypNonSecureRead(bool v = true) const
{
info[MISCREG_HYP_NS_RD] = v;
entry.info[MISCREG_HYP_NS_RD] = v;
return *this;
}
chain
@@ -1413,13 +1414,13 @@ namespace ArmISA
chain
hypSecureWrite(bool v = true) const
{
info[MISCREG_HYP_S_WR] = v;
entry.info[MISCREG_HYP_S_WR] = v;
return *this;
}
chain
hypNonSecureWrite(bool v = true) const
{
info[MISCREG_HYP_NS_WR] = v;
entry.info[MISCREG_HYP_NS_WR] = v;
return *this;
}
chain
@@ -1449,13 +1450,13 @@ namespace ArmISA
chain
monE2HRead(bool v = true) const
{
info[MISCREG_MON_E2H_RD] = v;
entry.info[MISCREG_MON_E2H_RD] = v;
return *this;
}
chain
monE2HWrite(bool v = true) const
{
info[MISCREG_MON_E2H_WR] = v;
entry.info[MISCREG_MON_E2H_WR] = v;
return *this;
}
chain
@@ -1469,28 +1470,28 @@ namespace ArmISA
monSecureRead(bool v = true) const
{
monE2HRead(v);
info[MISCREG_MON_NS0_RD] = v;
entry.info[MISCREG_MON_NS0_RD] = v;
return *this;
}
chain
monSecureWrite(bool v = true) const
{
monE2HWrite(v);
info[MISCREG_MON_NS0_WR] = v;
entry.info[MISCREG_MON_NS0_WR] = v;
return *this;
}
chain
monNonSecureRead(bool v = true) const
{
monE2HRead(v);
info[MISCREG_MON_NS1_RD] = v;
entry.info[MISCREG_MON_NS1_RD] = v;
return *this;
}
chain
monNonSecureWrite(bool v = true) const
{
monE2HWrite(v);
info[MISCREG_MON_NS1_WR] = v;
entry.info[MISCREG_MON_NS1_WR] = v;
return *this;
}
chain
@@ -1590,10 +1591,8 @@ namespace ArmISA
return *this;
}
chain highest(ArmSystem *const sys) const;
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e,
std::bitset<NUM_MISCREG_INFOS> &i)
: entry(e),
info(i)
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
: entry(e)
{
// force unimplemented registers to be thusly declared
implemented(1);
@@ -1601,7 +1600,6 @@ namespace ArmISA
};
extern std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
struct MiscRegNum32
{