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arch-mips: Convert float, int, and misc regs.

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Convert them to use namespaces, style guide compliant names, and (except
for misc regs) the new accessors.

Change-Id: I6f190658447d40b9933e498ce766ac6c629b6cbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49761
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-24 21:29:00 -07:00
parent 72290f00fd
commit 93fa99041d
19 changed files with 650 additions and 445 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/arch/mips/faults.cc
View File

@@ -100,32 +100,32 @@ void
MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
{
// modify SRS Ctl - Save CSS, put ESS into CSS
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
StatusReg status = tc->readMiscReg(misc_reg::Status);
if (status.exl != 1 && status.bev != 1) {
// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
SRSCtlReg srsCtl = tc->readMiscReg(misc_reg::Srsctl);
srsCtl.pss = srsCtl.css;
srsCtl.css = srsCtl.ess;
tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
tc->setMiscRegNoEffect(misc_reg::Srsctl, srsCtl);
}
// set EXL bit (don't care if it is already set!)
status.exl = 1;
tc->setMiscRegNoEffect(MISCREG_STATUS, status);
tc->setMiscRegNoEffect(misc_reg::Status, status);
// write EPC
auto pc = tc->pcState().as<PCState>();
DPRINTF(MipsPRA, "PC: %s\n", pc);
bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
tc->setMiscRegNoEffect(MISCREG_EPC,
tc->setMiscRegNoEffect(misc_reg::Epc,
pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
// Set Cause_EXCCODE field
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
CauseReg cause = tc->readMiscReg(misc_reg::Cause);
cause.excCode = excCode;
cause.bd = delay_slot ? 1 : 0;
cause.ce = 0;
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
tc->setMiscRegNoEffect(misc_reg::Cause, cause);
}
void
@@ -152,9 +152,9 @@ ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
}
// Set Coprocessor 1 (Floating Point) To Usable
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
StatusReg status = tc->readMiscRegNoEffect(misc_reg::Status);
status.cu.cu1 = 1;
tc->setMiscReg(MISCREG_STATUS, status);
tc->setMiscReg(misc_reg::Status, status);
}
void

24
src/arch/mips/faults.hh
View File

@@ -89,9 +89,9 @@ class MipsFaultBase : public FaultBase
virtual ExcCode code() const = 0;
virtual FaultVect base(ThreadContext *tc) const
{
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
StatusReg status = tc->readMiscReg(misc_reg::Status);
if (!status.bev)
return tc->readMiscReg(MISCREG_EBASE);
return tc->readMiscReg(misc_reg::Ebase);
else
return 0xbfc00200;
}
@@ -167,9 +167,9 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
CauseReg cause = tc->readMiscReg(misc_reg::Cause);
cause.ce = coProcID;
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
tc->setMiscRegNoEffect(misc_reg::Cause, cause);
}
}
};
@@ -180,7 +180,7 @@ class InterruptFault : public MipsFault<InterruptFault>
FaultVect
offset(ThreadContext *tc) const
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
CauseReg cause = tc->readMiscRegNoEffect(misc_reg::Cause);
// offset 0x200 for release 2, 0x180 for release 1.
return cause.iv ? 0x200 : 0x180;
}
@@ -202,7 +202,7 @@ class AddressFault : public MipsFault<T>
{
MipsFault<T>::invoke(tc, inst);
if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
tc->setMiscRegNoEffect(misc_reg::Badvaddr, vaddr);
}
};
@@ -237,16 +237,16 @@ class TlbFault : public AddressFault<T>
{
this->setExceptionState(tc, excCode);
tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
tc->setMiscRegNoEffect(misc_reg::Badvaddr, this->vaddr);
EntryHiReg entryHi = tc->readMiscReg(misc_reg::Entryhi);
entryHi.asid = this->asid;
entryHi.vpn2 = this->vpn >> 2;
entryHi.vpn2x = this->vpn & 0x3;
tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
tc->setMiscRegNoEffect(misc_reg::Entryhi, entryHi);
ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
ContextReg context = tc->readMiscReg(misc_reg::Context);
context.badVPN2 = this->vpn >> 2;
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
tc->setMiscRegNoEffect(misc_reg::Context, context);
}
void
@@ -280,7 +280,7 @@ class TlbRefillFault : public TlbFault<TlbRefillFault>
FaultVect
offset(ThreadContext *tc) const
{
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
StatusReg status = tc->readMiscReg(misc_reg::Status);
return status.exl ? 0x180 : 0x000;
}
};

20
src/arch/mips/interrupts.cc
View File

@@ -63,16 +63,16 @@ enum InterruptLevels
static inline uint8_t
getCauseIP(ThreadContext *tc)
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
CauseReg cause = tc->readMiscRegNoEffect(misc_reg::Cause);
return cause.ip;
}
static inline void
setCauseIP(ThreadContext *tc, uint8_t val)
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
CauseReg cause = tc->readMiscRegNoEffect(misc_reg::Cause);
cause.ip = val;
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
tc->setMiscRegNoEffect(misc_reg::Cause, cause);
}
void
@@ -127,14 +127,14 @@ Interrupts::checkInterrupts() const
return false;
//Check if there are any outstanding interrupts
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
StatusReg status = tc->readMiscRegNoEffect(misc_reg::Status);
// Interrupts must be enabled, error level must be 0 or interrupts
// inhibited, and exception level must be 0 or interrupts inhibited
if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
// Software interrupts & hardware interrupts are handled in software.
// So if any interrupt that isn't masked is detected, jump to interrupt
// handler
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
CauseReg cause = tc->readMiscRegNoEffect(misc_reg::Cause);
if (status.im && cause.ip)
return true;
@@ -149,8 +149,8 @@ Interrupts::getInterrupt()
assert(checkInterrupts());
[[maybe_unused]] StatusReg status =
tc->readMiscRegNoEffect(MISCREG_STATUS);
[[maybe_unused]] CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
tc->readMiscRegNoEffect(misc_reg::Status);
[[maybe_unused]] CauseReg cause = tc->readMiscRegNoEffect(misc_reg::Cause);
DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
(unsigned)status.im, (unsigned)cause.ip);
@@ -160,8 +160,8 @@ Interrupts::getInterrupt()
bool
Interrupts::onCpuTimerInterrupt() const
{
RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
RegVal compare = tc->readMiscRegNoEffect(misc_reg::Compare);
RegVal count = tc->readMiscRegNoEffect(misc_reg::Count);
if (compare == count && count != 0)
return true;
return false;
@@ -177,7 +177,7 @@ Interrupts::interruptsPending() const
if (onCpuTimerInterrupt()) {
DPRINTF(Interrupt, "Interrupts OnCpuTimerInterrupt() == true\n");
//determine timer interrupt IP #
IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
IntCtlReg intCtl = tc->readMiscRegNoEffect(misc_reg::Intctl);
uint8_t intStatus = getCauseIP(tc);
intStatus |= 1 << intCtl.ipti;
setCauseIP(tc, intStatus);

186
src/arch/mips/isa.cc
View File

@@ -51,7 +51,7 @@ namespace MipsISA
{
std::string
ISA::miscRegNames[MISCREG_NUMREGS] =
ISA::miscRegNames[misc_reg::NumRegs] =
{
"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
"Random", "VPEControl", "VPEConf0", "VPEConf1",
@@ -100,37 +100,37 @@ ISA::miscRegNames[MISCREG_NUMREGS] =
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
_regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(0, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(MISCREG_NUMREGS, debug::MiscRegs);
_regClasses.emplace_back(misc_reg::NumRegs, debug::MiscRegs);
miscRegFile.resize(MISCREG_NUMREGS);
bankType.resize(MISCREG_NUMREGS);
miscRegFile.resize(misc_reg::NumRegs);
bankType.resize(misc_reg::NumRegs);
for (int i = 0; i < MISCREG_NUMREGS; i++) {
for (int i = 0; i < misc_reg::NumRegs; i++) {
miscRegFile[i].resize(1);
bankType[i] = perProcessor;
}
miscRegFile_WriteMask.resize(MISCREG_NUMREGS);
miscRegFile_WriteMask.resize(misc_reg::NumRegs);
for (int i = 0; i < MISCREG_NUMREGS; i++) {
for (int i = 0; i < misc_reg::NumRegs; i++) {
miscRegFile_WriteMask[i].push_back(0);
}
// Initialize all Per-VPE regs
uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
MISCREG_YQMASK,
MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
MISCREG_EBASE
uint32_t per_vpe_regs[] = { misc_reg::VpeControl,
misc_reg::VpeConf0, misc_reg::VpeConf1,
misc_reg::Yqmask,
misc_reg::VpeSchedule, misc_reg::VpeSchefback,
misc_reg::VpeOpt, misc_reg::SrsConf0,
misc_reg::SrsConf1, misc_reg::SrsConf2,
misc_reg::SrsConf3, misc_reg::SrsConf4,
misc_reg::Ebase
};
uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
for (int i = 0; i < num_vpe_regs; i++) {
@@ -141,12 +141,12 @@ ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
}
// Initialize all Per-TC regs
uint32_t per_tc_regs[] = { MISCREG_STATUS,
MISCREG_TC_STATUS, MISCREG_TC_BIND,
MISCREG_TC_RESTART, MISCREG_TC_HALT,
MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
MISCREG_TC_SCHEFBACK,
MISCREG_DEBUG, MISCREG_LLADDR
uint32_t per_tc_regs[] = { misc_reg::Status,
misc_reg::TcStatus, misc_reg::TcBind,
misc_reg::TcRestart, misc_reg::TcHalt,
misc_reg::TcContext, misc_reg::TcSchedule,
misc_reg::TcSchefback,
misc_reg::Debug, misc_reg::Lladdr
};
uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
@@ -161,7 +161,7 @@ ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
void
ISA::clear()
{
for (int i = 0; i < MISCREG_NUMREGS; i++) {
for (int i = 0; i < misc_reg::NumRegs; i++) {
for (int j = 0; j < miscRegFile[i].size(); j++)
miscRegFile[i][j] = 0;
@@ -174,15 +174,19 @@ void
ISA::copyRegsFrom(ThreadContext *src)
{
// First loop through the integer registers.
for (int i = 0; i < NumIntRegs; i++)
tc->setIntRegFlat(i, src->readIntRegFlat(i));
for (int i = 0; i < int_reg::NumRegs; i++) {
RegId reg(IntRegClass, i);
tc->setRegFlat(reg, src->getRegFlat(reg));
}
// Then loop through the floating point registers.
for (int i = 0; i < NumFloatRegs; i++)
tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
for (int i = 0; i < float_reg::NumRegs; i++) {
RegId reg(FloatRegClass, i);
tc->setRegFlat(reg, src->getRegFlat(reg));
}
// Copy misc. registers
for (int i = 0; i < MISCREG_NUMREGS; i++)
for (int i = 0; i < misc_reg::NumRegs; i++)
tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
// Copy over the PC State
@@ -206,34 +210,34 @@ ISA::configCP()
// ===================================================
DPRINTF(MipsPRA, "Initializing CP0 State.... ");
PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
PRIdReg procId = readMiscRegNoEffect(misc_reg::Prid);
procId.coOp = cp.CP0_PRId_CompanyOptions;
procId.coId = cp.CP0_PRId_CompanyID;
procId.procId = cp.CP0_PRId_ProcessorID;
procId.rev = cp.CP0_PRId_Revision;
setMiscRegNoEffect(MISCREG_PRID, procId);
setMiscRegNoEffect(misc_reg::Prid, procId);
// Now, create Write Mask for ProcID register
RegVal procIDMask = 0; // Read-Only register
replaceBits(procIDMask, 32, 0, 0);
setRegMask(MISCREG_PRID, procIDMask);
setRegMask(misc_reg::Prid, procIDMask);
// Config
ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
ConfigReg cfg = readMiscRegNoEffect(misc_reg::Config);
cfg.be = cp.CP0_Config_BE;
cfg.at = cp.CP0_Config_AT;
cfg.ar = cp.CP0_Config_AR;
cfg.mt = cp.CP0_Config_MT;
cfg.vi = cp.CP0_Config_VI;
cfg.m = 1;
setMiscRegNoEffect(MISCREG_CONFIG, cfg);
setMiscRegNoEffect(misc_reg::Config, cfg);
// Now, create Write Mask for Config register
RegVal cfg_Mask = 0x7FFF0007;
replaceBits(cfg_Mask, 32, 0, 0);
setRegMask(MISCREG_CONFIG, cfg_Mask);
setRegMask(misc_reg::Config, cfg_Mask);
// Config1
Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
Config1Reg cfg1 = readMiscRegNoEffect(misc_reg::Config1);
cfg1.mmuSize = cp.CP0_Config1_MMU;
cfg1.is = cp.CP0_Config1_IS;
cfg1.il = cp.CP0_Config1_IL;
@@ -248,14 +252,14 @@ ISA::configCP()
cfg1.c2 = cp.CP0_Config1_C2;
cfg1.pc = cp.CP0_Config1_PC;
cfg1.m = cp.CP0_Config1_M;
setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
setMiscRegNoEffect(misc_reg::Config1, cfg1);
// Now, create Write Mask for Config register
RegVal cfg1_Mask = 0; // Read Only Register
replaceBits(cfg1_Mask, 32,0 , 0);
setRegMask(MISCREG_CONFIG1, cfg1_Mask);
setRegMask(misc_reg::Config1, cfg1_Mask);
// Config2
Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
Config2Reg cfg2 = readMiscRegNoEffect(misc_reg::Config2);
cfg2.tu = cp.CP0_Config2_TU;
cfg2.ts = cp.CP0_Config2_TS;
cfg2.tl = cp.CP0_Config2_TL;
@@ -265,14 +269,14 @@ ISA::configCP()
cfg2.sl = cp.CP0_Config2_SL;
cfg2.sa = cp.CP0_Config2_SA;
cfg2.m = cp.CP0_Config2_M;
setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
setMiscRegNoEffect(misc_reg::Config2, cfg2);
// Now, create Write Mask for Config register
RegVal cfg2_Mask = 0x7000F000; // Read Only Register
replaceBits(cfg2_Mask, 32, 0, 0);
setRegMask(MISCREG_CONFIG2, cfg2_Mask);
setRegMask(misc_reg::Config2, cfg2_Mask);
// Config3
Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
Config3Reg cfg3 = readMiscRegNoEffect(misc_reg::Config3);
cfg3.dspp = cp.CP0_Config3_DSPP;
cfg3.lpa = cp.CP0_Config3_LPA;
cfg3.veic = cp.CP0_Config3_VEIC;
@@ -281,79 +285,79 @@ ISA::configCP()
cfg3.mt = cp.CP0_Config3_MT;
cfg3.sm = cp.CP0_Config3_SM;
cfg3.tl = cp.CP0_Config3_TL;
setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
setMiscRegNoEffect(misc_reg::Config3, cfg3);
// Now, create Write Mask for Config register
RegVal cfg3_Mask = 0; // Read Only Register
replaceBits(cfg3_Mask, 32,0 , 0);
setRegMask(MISCREG_CONFIG3, cfg3_Mask);
setRegMask(misc_reg::Config3, cfg3_Mask);
// EBase - CPUNum
EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
EBaseReg eBase = readMiscRegNoEffect(misc_reg::Ebase);
eBase.cpuNum = cp.CP0_EBase_CPUNum;
replaceBits(eBase, 31, 31, 1);
setMiscRegNoEffect(MISCREG_EBASE, eBase);
setMiscRegNoEffect(misc_reg::Ebase, eBase);
// Now, create Write Mask for Config register
RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
// entire register is read only
replaceBits(EB_Mask, 32, 0, 0);
setRegMask(MISCREG_EBASE, EB_Mask);
setRegMask(misc_reg::Ebase, EB_Mask);
// SRS Control - HSS (Highest Shadow Set)
SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
SRSCtlReg scsCtl = readMiscRegNoEffect(misc_reg::Srsctl);
scsCtl.hss = cp.CP0_SrsCtl_HSS;
setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
setMiscRegNoEffect(misc_reg::Srsctl, scsCtl);
// Now, create Write Mask for the SRS Ctl register
RegVal SC_Mask = 0x0000F3C0;
replaceBits(SC_Mask, 32, 0, 0);
setRegMask(MISCREG_SRSCTL, SC_Mask);
setRegMask(misc_reg::Srsctl, SC_Mask);
// IntCtl - IPTI, IPPCI
IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
IntCtlReg intCtl = readMiscRegNoEffect(misc_reg::Intctl);
intCtl.ipti = cp.CP0_IntCtl_IPTI;
intCtl.ippci = cp.CP0_IntCtl_IPPCI;
setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
setMiscRegNoEffect(misc_reg::Intctl, intCtl);
// Now, create Write Mask for the IntCtl register
RegVal IC_Mask = 0x000003E0;
replaceBits(IC_Mask, 32, 0, 0);
setRegMask(MISCREG_INTCTL, IC_Mask);
setRegMask(misc_reg::Intctl, IC_Mask);
// Watch Hi - M - FIXME (More than 1 Watch register)
WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
WatchHiReg watchHi = readMiscRegNoEffect(misc_reg::Watchhi0);
watchHi.m = cp.CP0_WatchHi_M;
setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
setMiscRegNoEffect(misc_reg::Watchhi0, watchHi);
// Now, create Write Mask for the IntCtl register
RegVal wh_Mask = 0x7FFF0FFF;
replaceBits(wh_Mask, 32, 0, 0);
setRegMask(MISCREG_WATCHHI0, wh_Mask);
setRegMask(misc_reg::Watchhi0, wh_Mask);
// Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(misc_reg::Perfcnt0);
perfCntCtl.m = cp.CP0_PerfCtr_M;
perfCntCtl.w = cp.CP0_PerfCtr_W;
setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
setMiscRegNoEffect(misc_reg::Perfcnt0, perfCntCtl);
// Now, create Write Mask for the IntCtl register
RegVal pc_Mask = 0x00007FF;
replaceBits(pc_Mask, 32, 0, 0);
setRegMask(MISCREG_PERFCNT0, pc_Mask);
setRegMask(misc_reg::Perfcnt0, pc_Mask);
// Random
setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
setMiscRegNoEffect(misc_reg::Cp0Random, 63);
// Now, create Write Mask for the IntCtl register
RegVal random_Mask = 0;
replaceBits(random_Mask, 32, 0, 0);
setRegMask(MISCREG_CP0_RANDOM, random_Mask);
setRegMask(misc_reg::Cp0Random, random_Mask);
// PageGrain
PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
PageGrainReg pageGrain = readMiscRegNoEffect(misc_reg::Pagegrain);
pageGrain.esp = cp.CP0_Config3_SP;
setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
setMiscRegNoEffect(misc_reg::Pagegrain, pageGrain);
// Now, create Write Mask for the IntCtl register
RegVal pg_Mask = 0x10000000;
replaceBits(pg_Mask, 32, 0, 0);
setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
setRegMask(misc_reg::Pagegrain, pg_Mask);
// Status
StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
StatusReg status = readMiscRegNoEffect(misc_reg::Status);
// Only CU0 and IE are modified on a reset - everything else needs
// to be controlled on a per CPU model basis
@@ -365,47 +369,47 @@ ISA::configCP()
// Enable BEV bit on a reset
status.bev = 1;
setMiscRegNoEffect(MISCREG_STATUS, status);
setMiscRegNoEffect(misc_reg::Status, status);
// Now, create Write Mask for the Status register
RegVal stat_Mask = 0xFF78FF17;
replaceBits(stat_Mask, 32, 0, 0);
setRegMask(MISCREG_STATUS, stat_Mask);
setRegMask(misc_reg::Status, stat_Mask);
// MVPConf0
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(misc_reg::MvpConf0);
mvpConf0.tca = 1;
mvpConf0.pvpe = numVpes - 1;
mvpConf0.ptc = numThreads - 1;
setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
setMiscRegNoEffect(misc_reg::MvpConf0, mvpConf0);
// VPEConf0
VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
VPEConf0Reg vpeConf0 = readMiscRegNoEffect(misc_reg::VpeConf0);
vpeConf0.mvp = 1;
setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
setMiscRegNoEffect(misc_reg::VpeConf0, vpeConf0);
// TCBind
for (ThreadID tid = 0; tid < numThreads; tid++) {
TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
TCBindReg tcBind = readMiscRegNoEffect(misc_reg::TcBind, tid);
tcBind.curTC = tid;
setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
setMiscRegNoEffect(misc_reg::TcBind, tcBind, tid);
}
// TCHalt
TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
TCHaltReg tcHalt = readMiscRegNoEffect(misc_reg::TcHalt);
tcHalt.h = 0;
setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
setMiscRegNoEffect(misc_reg::TcHalt, tcHalt);
// TCStatus
// Set TCStatus Activated to 1 for the initial thread that is running
TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
TCStatusReg tcStatus = readMiscRegNoEffect(misc_reg::TcStatus);
tcStatus.a = 1;
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
setMiscRegNoEffect(misc_reg::TcStatus, tcStatus);
// Set Dynamically Allocatable bit to 1 for all other threads
for (ThreadID tid = 1; tid < numThreads; tid++) {
tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
tcStatus = readMiscRegNoEffect(misc_reg::TcStatus, tid);
tcStatus.da = 1;
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
setMiscRegNoEffect(misc_reg::TcStatus, tcStatus, tid);
}
@@ -413,36 +417,36 @@ ISA::configCP()
// Now, create Write Mask for the Index register
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_INDEX, mask);
setRegMask(misc_reg::Index, mask);
mask = 0x3FFFFFFF;
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_ENTRYLO0, mask);
setRegMask(MISCREG_ENTRYLO1, mask);
setRegMask(misc_reg::Entrylo0, mask);
setRegMask(misc_reg::Entrylo1, mask);
mask = 0xFF800000;
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_CONTEXT, mask);
setRegMask(misc_reg::Context, mask);
mask = 0x1FFFF800;
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_PAGEMASK, mask);
setRegMask(misc_reg::Pagemask, mask);
mask = 0x0;
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_BADVADDR, mask);
setRegMask(MISCREG_LLADDR, mask);
setRegMask(misc_reg::Badvaddr, mask);
setRegMask(misc_reg::Lladdr, mask);
mask = 0x08C00300;
replaceBits(mask, 32, 0, 0);
setRegMask(MISCREG_CAUSE, mask);
setRegMask(misc_reg::Cause, mask);
}
inline unsigned
ISA::getVPENum(ThreadID tid) const
{
TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
TCBindReg tcBind = miscRegFile[misc_reg::TcBind][tid];
return tcBind.curVPE;
}
@@ -566,12 +570,12 @@ ISA::updateCPU(BaseCPU *cpu)
// EVALUATE CP0 STATE FOR MIPS MT
//
///////////////////////////////////////////////////////////////////
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(misc_reg::MvpConf0);
ThreadID num_threads = mvpConf0.ptc + 1;
for (ThreadID tid = 0; tid < num_threads; tid++) {
TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
TCStatusReg tcStatus = readMiscRegNoEffect(misc_reg::TcStatus, tid);
TCHaltReg tcHalt = readMiscRegNoEffect(misc_reg::TcHalt, tid);
//@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
if (tcHalt.h == 1 || tcStatus.a == 0) {

6
src/arch/mips/isa.hh
View File

@@ -137,7 +137,7 @@ namespace MipsISA
// and if necessary alert the CPU
void updateCPU(BaseCPU *cpu);
static std::string miscRegNames[MISCREG_NUMREGS];
static std::string miscRegNames[misc_reg::NumRegs];
public:
ISA(const Params &p);
@@ -156,8 +156,8 @@ namespace MipsISA
bool
inUserMode() const override
{
RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS);
RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG);
RegVal Stat = readMiscRegNoEffect(misc_reg::Status);
RegVal Dbg = readMiscRegNoEffect(misc_reg::Debug);
if (// EXL, ERL or CU0 set, CP0 accessible
(Stat & 0x10000006) == 0 &&

59
src/arch/mips/isa/decoder.isa
View File

@@ -393,55 +393,55 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode RT {
0x0: mftlo_dsp0({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO0));
int_reg::DspLo0);
}});
0x1: mfthi_dsp0({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI0));
int_reg::DspHi0);
}});
0x2: mftacx_dsp0({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX0));
int_reg::DspAcx0);
}});
0x4: mftlo_dsp1({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO1));
int_reg::DspLo1);
}});
0x5: mfthi_dsp1({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI1));
int_reg::DspHi1);
}});
0x6: mftacx_dsp1({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX1));
int_reg::DspAcx1);
}});
0x8: mftlo_dsp2({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO2));
int_reg::DspLo2);
}});
0x9: mfthi_dsp2({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI2));
int_reg::DspHi2);
}});
0x10: mftacx_dsp2({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX2));
int_reg::DspAcx2);
}});
0x12: mftlo_dsp3({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO3));
int_reg::DspLo3);
}});
0x13: mfthi_dsp3({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI3));
int_reg::DspHi3);
}});
0x14: mftacx_dsp3({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX3));
int_reg::DspAcx3);
}});
0x16: mftdsp({{
data = readRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_CONTROL));
int_reg::DspControl);
}});
default: CP0Unimpl::unknown();
}
@@ -457,11 +457,11 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x3: cftc1({{
uint32_t fcsr_val = readRegOtherThread(xc,
RegId(FloatRegClass, FLOATREG_FCSR));
float_reg::Fcsr);
switch (RT) {
case 0:
data = readRegOtherThread(xc,
RegId(MiscRegClass, FLOATREG_FIR));
float_reg::Fir);
break;
case 25:
data = (fcsr_val & 0xFE000000 >> 24) |
@@ -499,43 +499,43 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x1: decode RT {
0x0: mttlo_dsp0({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO0), Rt);
int_reg::DspLo0, Rt);
}});
0x1: mtthi_dsp0({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI0), Rt);
int_reg::DspHi0, Rt);
}});
0x2: mttacx_dsp0({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX0), Rt);
int_reg::DspAcx0, Rt);
}});
0x4: mttlo_dsp1({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO1), Rt);
int_reg::DspLo1, Rt);
}});
0x5: mtthi_dsp1({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI1), Rt);
int_reg::DspHi1, Rt);
}});
0x6: mttacx_dsp1({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX1), Rt);
int_reg::DspAcx1, Rt);
}});
0x8: mttlo_dsp2({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO2), Rt);
int_reg::DspLo2, Rt);
}});
0x9: mtthi_dsp2({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI2), Rt);
int_reg::DspHi2, Rt);
}});
0x10: mttacx_dsp2({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX2), Rt);
int_reg::DspAcx2, Rt);
}});
0x12: mttlo_dsp3({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_LO3), Rt);
int_reg::DspLo3, Rt);
}});
0x13: mtthi_dsp3({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_HI3), Rt);
int_reg::DspHi3, Rt);
}});
0x14: mttacx_dsp3({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_ACX3), Rt);
int_reg::DspAcx3, Rt);
}});
0x16: mttdsp({{ setRegOtherThread(xc,
RegId(IntRegClass, INTREG_DSP_CONTROL), Rt);
int_reg::DspControl, Rt);
}});
default: CP0Unimpl::unknown();
@@ -582,8 +582,7 @@ decode OPCODE_HI default Unknown::unknown() {
"Access to Floating Control "
"S""tatus Register", FS);
}
setRegOtherThread(xc,
RegId(FloatRegClass, FLOATREG_FCSR), data);
setRegOtherThread(xc, float_reg::Fcsr, data);
}});
default: CP0Unimpl::unknown();
}

10
src/arch/mips/isa/formats/control.isa
View File

@@ -177,9 +177,9 @@ output exec {{
if (!FullSystem)
return true;
RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
RegVal Stat = xc->readMiscReg(misc_reg::Status);
if (cop_num == 0) {
RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
RegVal Dbg = xc->readMiscReg(misc_reg::Debug);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
// In Dbg, DM bit set, CP0 accessible
// In Stat, KSU = 0, kernel mode is base mode
@@ -197,8 +197,8 @@ output exec {{
isCoprocessor0Enabled(ExecContext *xc)
{
if (FullSystem) {
RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
RegVal Stat = xc->readMiscReg(misc_reg::Status);
RegVal Dbg = xc->readMiscReg(misc_reg::Debug);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
// In Dbg, DM bit set, CP0 accessible
// In Stat KSU = 0, kernel mode is base mode
@@ -212,7 +212,7 @@ output exec {{
bool
isMMUTLB(ExecContext *xc)
{
RegVal Config = xc->readMiscReg(MISCREG_CONFIG);
RegVal Config = xc->readMiscReg(misc_reg::Config);
return FullSystem && (Config & 0x380) == 0x80;
}
}};

4
src/arch/mips/isa/formats/dsp.isa
View File

@@ -147,7 +147,7 @@ output exec {{
bool
isDspEnabled(ExecContext *xc)
{
return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
return !FullSystem || bits(xc->readMiscReg(misc_reg::Status), 24);
}
}};
@@ -155,7 +155,7 @@ output exec {{
bool
isDspPresent(ExecContext *xc)
{
return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
return !FullSystem || bits(xc->readMiscReg(misc_reg::Config3), 10);
}
}};

9
src/arch/mips/isa/formats/fp.isa
View File

@@ -132,13 +132,12 @@ output exec {{
cpu->setRegOperand(inst, 0, mips_nan);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits =
cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
uint32_t fcsr_bits = cpu->tcBase()->getReg(float_reg::Fcsr);
uint32_t new_fcsr = genInvalidVector(fcsr_bits);
//Write FCSR from FloatRegFile
cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr);
cpu->tcBase()->setReg(float_reg::Fcsr, new_fcsr);
if (traceData) { traceData->setData(mips_nan); }
return true;
@@ -151,13 +150,13 @@ output exec {{
fpResetCauseBits(ExecContext *cpu)
{
//Read FCSR from FloatRegFile
uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
uint32_t fcsr = cpu->tcBase()->getReg(float_reg::Fcsr);
// TODO: Use utility function here
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
//Write FCSR from FloatRegFile
cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr);
cpu->tcBase()->setReg(float_reg::Fcsr, fcsr);
}
}};

12
src/arch/mips/isa/formats/mt.isa
View File

@@ -92,17 +92,17 @@ output exec {{
TCBindReg &tc_bind, VPEControlReg &vpe_control,
MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
vpe_conf0 = xc->readMiscReg(misc_reg::VpeConf0);
tc_bind_mt = readRegOtherThread(xc, RegId(MiscRegClass,
MISCREG_TC_BIND));
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
misc_reg::TcBind));
tc_bind = xc->readMiscReg(misc_reg::TcBind);
vpe_control = xc->readMiscReg(misc_reg::VpeControl);
mvp_conf0 = xc->readMiscReg(misc_reg::MvpConf0);
}
void getMTExValues(ExecContext *xc, Config3Reg &config3)
{
config3 = xc->readMiscReg(MISCREG_CONFIG3);
config3 = xc->readMiscReg(misc_reg::Config3);
}
}};

106
src/arch/mips/isa/operands.isa
View File

@@ -60,29 +60,29 @@ def operands {{
'R31': IntReg('uw', '31', 'IsInteger', 4),
#Special Integer Reg operands
'LO0': IntReg('uw', 'INTREG_LO', 'IsInteger', 6),
'HI0': IntReg('uw', 'INTREG_HI', 'IsInteger', 7),
'LO0': IntReg('uw', 'int_reg::Lo', 'IsInteger', 6),
'HI0': IntReg('uw', 'int_reg::Hi', 'IsInteger', 7),
#Bitfield-dependent HI/LO Register Access
'LO_RD_SEL': IntReg('uw', 'INTREG_DSP_LO0 + ACDST*3', None, 6),
'HI_RD_SEL': IntReg('uw', 'INTREG_DSP_HI0 + ACDST*3', None, 7),
'LO_RS_SEL': IntReg('uw', 'INTREG_DSP_LO0 + ACSRC*3', None, 6),
'HI_RS_SEL': IntReg('uw', 'INTREG_DSP_HI0 + ACSRC*3', None, 7),
'LO_RD_SEL': IntReg('uw', 'int_reg::DspLo0 + ACDST*3', None, 6),
'HI_RD_SEL': IntReg('uw', 'int_reg::DspHi0 + ACDST*3', None, 7),
'LO_RS_SEL': IntReg('uw', 'int_reg::DspLo0 + ACSRC*3', None, 6),
'HI_RS_SEL': IntReg('uw', 'int_reg::DspHi0 + ACSRC*3', None, 7),
#DSP Special Purpose Integer Operands
'DSPControl': IntReg('uw', 'INTREG_DSP_CONTROL', None, 8),
'DSPLo0': IntReg('uw', 'INTREG_LO', None, 1),
'DSPHi0': IntReg('uw', 'INTREG_HI', None, 1),
'DSPACX0': IntReg('uw', 'INTREG_DSP_ACX0', None, 1),
'DSPLo1': IntReg('uw', 'INTREG_DSP_LO1', None, 1),
'DSPHi1': IntReg('uw', 'INTREG_DSP_HI1', None, 1),
'DSPACX1': IntReg('uw', 'INTREG_DSP_ACX1', None, 1),
'DSPLo2': IntReg('uw', 'INTREG_DSP_LO2', None, 1),
'DSPHi2': IntReg('uw', 'INTREG_DSP_HI2', None, 1),
'DSPACX2': IntReg('uw', 'INTREG_DSP_ACX2', None, 1),
'DSPLo3': IntReg('uw', 'INTREG_DSP_LO3', None, 1),
'DSPHi3': IntReg('uw', 'INTREG_DSP_HI3', None, 1),
'DSPACX3': IntReg('uw', 'INTREG_DSP_ACX3', None, 1),
'DSPControl': IntReg('uw', 'int_reg::DspControl', None, 8),
'DSPLo0': IntReg('uw', 'int_reg::Lo', None, 1),
'DSPHi0': IntReg('uw', 'int_reg::Hi', None, 1),
'DSPACX0': IntReg('uw', 'int_reg::DspAcx0', None, 1),
'DSPLo1': IntReg('uw', 'int_reg::DspLo1', None, 1),
'DSPHi1': IntReg('uw', 'int_reg::DspHi1', None, 1),
'DSPACX1': IntReg('uw', 'int_reg::DspAcx1', None, 1),
'DSPLo2': IntReg('uw', 'int_reg::DspLo2', None, 1),
'DSPHi2': IntReg('uw', 'int_reg::DspHi2', None, 1),
'DSPACX2': IntReg('uw', 'int_reg::DspAcx2', None, 1),
'DSPLo3': IntReg('uw', 'int_reg::DspLo3', None, 1),
'DSPHi3': IntReg('uw', 'int_reg::DspHi3', None, 1),
'DSPACX3': IntReg('uw', 'int_reg::DspAcx3', None, 1),
#Floating Point Reg Operands
'Fd': FloatRegOp('sf', 'FD', 'IsFloating', 1),
@@ -91,11 +91,11 @@ def operands {{
'Fr': FloatRegOp('sf', 'FR', 'IsFloating', 3),
#Special Purpose Floating Point Control Reg Operands
'FIR': FloatRegOp('uw', 'FLOATREG_FIR', 'IsFloating', 1),
'FCCR': FloatRegOp('uw', 'FLOATREG_FCCR', 'IsFloating', 2),
'FEXR': FloatRegOp('uw', 'FLOATREG_FEXR', 'IsFloating', 3),
'FENR': FloatRegOp('uw', 'FLOATREG_FENR', 'IsFloating', 3),
'FCSR': FloatRegOp('uw', 'FLOATREG_FCSR', 'IsFloating', 3),
'FIR': FloatRegOp('uw', 'float_reg::Fir', 'IsFloating', 1),
'FCCR': FloatRegOp('uw', 'float_reg::Fccr', 'IsFloating', 2),
'FEXR': FloatRegOp('uw', 'float_reg::Fexr', 'IsFloating', 3),
'FENR': FloatRegOp('uw', 'float_reg::Fenr', 'IsFloating', 3),
'FCSR': FloatRegOp('uw', 'float_reg::Fcsr', 'IsFloating', 3),
#Operands For Paired Singles FP Operations
'Fd1': FloatRegOp('sf', 'FD', 'IsFloating', 4),
@@ -108,48 +108,48 @@ def operands {{
'Fr2': FloatRegOp('sf', 'FR+1', 'IsFloating', 7),
#Status Control Reg
'Status': ControlRegOp('uw', 'MISCREG_STATUS', None, 1),
'Status': ControlRegOp('uw', 'misc_reg::Status', None, 1),
#LL Flag
'LLFlag': ControlRegOp('uw', 'MISCREG_LLFLAG', None, 1),
'LLFlag': ControlRegOp('uw', 'misc_reg::Llflag', None, 1),
#Thread pointer value for SE mode
'TpValue': ControlRegOp('ud', 'MISCREG_TP_VALUE', None, 1),
'TpValue': ControlRegOp('ud', 'misc_reg::TpValue', None, 1),
# Index Register
'Index': ControlRegOp('uw','MISCREG_INDEX',None,1),
'Index': ControlRegOp('uw','misc_reg::Index',None,1),
'CP0_RD_SEL': ControlRegOp('uw', '(RD << 3 | SEL)', None, 1),
#MT Control Regs
'MVPConf0': ControlRegOp('uw', 'MISCREG_MVP_CONF0', None, 1),
'MVPControl': ControlRegOp('uw', 'MISCREG_MVP_CONTROL', None, 1),
'TCBind': ControlRegOp('uw', 'MISCREG_TC_BIND', None, 1),
'TCStatus': ControlRegOp('uw', 'MISCREG_TC_STATUS', None, 1),
'TCRestart': ControlRegOp('uw', 'MISCREG_TC_RESTART', None, 1),
'VPEConf0': ControlRegOp('uw', 'MISCREG_VPE_CONF0', None, 1),
'VPEControl': ControlRegOp('uw', 'MISCREG_VPE_CONTROL', None, 1),
'YQMask': ControlRegOp('uw', 'MISCREG_YQMASK', None, 1),
'MVPConf0': ControlRegOp('uw', 'misc_reg::MvpConf0', None, 1),
'MVPControl': ControlRegOp('uw', 'misc_reg::MvpControl', None, 1),
'TCBind': ControlRegOp('uw', 'misc_reg::TcBind', None, 1),
'TCStatus': ControlRegOp('uw', 'misc_reg::TcStatus', None, 1),
'TCRestart': ControlRegOp('uw', 'misc_reg::TcRestart', None, 1),
'VPEConf0': ControlRegOp('uw', 'misc_reg::VpeConf0', None, 1),
'VPEControl': ControlRegOp('uw', 'misc_reg::VpeControl', None, 1),
'YQMask': ControlRegOp('uw', 'misc_reg::Yqmask', None, 1),
#CP0 Control Regs
'EntryHi': ControlRegOp('uw', 'MISCREG_ENTRYHI',None,1),
'EntryLo0': ControlRegOp('uw', 'MISCREG_ENTRYLO0',None,1),
'EntryLo1': ControlRegOp('uw', 'MISCREG_ENTRYLO1',None,1),
'PageMask': ControlRegOp('uw', 'MISCREG_PAGEMASK',None,1),
'Random': ControlRegOp('uw', 'MISCREG_CP0_RANDOM',None,1),
'ErrorEPC': ControlRegOp('uw', 'MISCREG_ERROR_EPC',None,1),
'EPC': ControlRegOp('uw', 'MISCREG_EPC',None,1),
'DEPC': ControlRegOp('uw', 'MISCREG_DEPC',None,1),
'IntCtl': ControlRegOp('uw', 'MISCREG_INTCTL',None,1),
'SRSCtl': ControlRegOp('uw', 'MISCREG_SRSCTL',None,1),
'Config': ControlRegOp('uw', 'MISCREG_CONFIG',None,1),
'Config3': ControlRegOp('uw', 'MISCREG_CONFIG3',None,1),
'Config1': ControlRegOp('uw', 'MISCREG_CONFIG1',None,1),
'Config2': ControlRegOp('uw', 'MISCREG_CONFIG2',None,1),
'PageGrain': ControlRegOp('uw', 'MISCREG_PAGEGRAIN',None,1),
'Debug': ControlRegOp('uw', 'MISCREG_DEBUG',None,1),
'Cause': ControlRegOp('uw', 'MISCREG_CAUSE',None,1),
'EntryHi': ControlRegOp('uw', 'misc_reg::Entryhi',None,1),
'EntryLo0': ControlRegOp('uw', 'misc_reg::Entrylo0',None,1),
'EntryLo1': ControlRegOp('uw', 'misc_reg::Entrylo1',None,1),
'PageMask': ControlRegOp('uw', 'misc_reg::Pagemask',None,1),
'Random': ControlRegOp('uw', 'misc_reg::Cp0Random',None,1),
'ErrorEPC': ControlRegOp('uw', 'misc_reg::ErrorEpc',None,1),
'EPC': ControlRegOp('uw', 'misc_reg::Epc',None,1),
'DEPC': ControlRegOp('uw', 'misc_reg::Depc',None,1),
'IntCtl': ControlRegOp('uw', 'misc_reg::Intctl',None,1),
'SRSCtl': ControlRegOp('uw', 'misc_reg::Srsctl',None,1),
'Config': ControlRegOp('uw', 'misc_reg::Config',None,1),
'Config3': ControlRegOp('uw', 'misc_reg::Config3',None,1),
'Config1': ControlRegOp('uw', 'misc_reg::Config1',None,1),
'Config2': ControlRegOp('uw', 'misc_reg::Config2',None,1),
'PageGrain': ControlRegOp('uw', 'misc_reg::Pagegrain',None,1),
'Debug': ControlRegOp('uw', 'misc_reg::Debug',None,1),
'Cause': ControlRegOp('uw', 'misc_reg::Cause',None,1),
#Memory Operand
'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), 4),

4
src/arch/mips/linux/se_workload.cc
View File

@@ -82,7 +82,7 @@ EmuLinux::syscall(ThreadContext *tc)
// This will move into the base SEWorkload function at some point.
process->Process::syscall(tc);
syscallDescs.get(tc->readIntReg(2))->doSyscall(tc);
syscallDescs.get(tc->getReg(int_reg::V0))->doSyscall(tc);
}
/// Target uname() handler.
@@ -153,7 +153,7 @@ sys_setsysinfoFunc(SyscallDesc *desc, ThreadContext *tc, unsigned op,
static SyscallReturn
setThreadAreaFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> addr)
{
tc->setMiscRegNoEffect(MISCREG_TP_VALUE, addr);
tc->setMiscRegNoEffect(misc_reg::TpValue, addr);
return 0;
}

72
src/arch/mips/mt.hh
View File

@@ -65,10 +65,8 @@ readRegOtherThread(ThreadContext *tc, const RegId &reg,
switch (reg.classValue()) {
case IntRegClass:
return otc->readIntReg(reg.index());
break;
case FloatRegClass:
return otc->readFloatReg(reg.index());
return otc->getReg(reg);
break;
case MiscRegClass:
return otc->readMiscReg(reg.index());
@@ -89,10 +87,8 @@ setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val,
switch (reg.classValue()) {
case IntRegClass:
return otc->setIntReg(reg.index(), val);
break;
case FloatRegClass:
return otc->setFloatReg(reg.index(), val);
otc->setReg(reg, val);
break;
case MiscRegClass:
return otc->setMiscReg(reg.index(), val);
@@ -119,7 +115,7 @@ template <class TC>
inline unsigned
getVirtProcNum(TC *tc)
{
TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
TCBindReg tcbind = tc->readMiscRegNoEffect(misc_reg::TcBind);
return tcbind.curVPE;
}
@@ -127,7 +123,7 @@ template <class TC>
inline unsigned
getTargetThread(TC *tc)
{
VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(misc_reg::VpeControl);
return vpeCtrl.targTC;
}
@@ -142,7 +138,7 @@ haltThread(TC *tc)
// @TODO: Needs to check if this is a branch and if so,
// take previous instruction
auto &pc = tc->pcState().template as<MipsISA::PCState>();
tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
tc->setMiscReg(misc_reg::TcRestart, pc.npc());
warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
curTick(), tc->threadId(), tc->getCpuPtr()->name(),
@@ -156,7 +152,7 @@ restoreThread(TC *tc)
{
if (tc->status() != TC::Active) {
// Restore PC from TCRestart
Addr restartPC = tc->readMiscRegNoEffect(MISCREG_TC_RESTART);
Addr restartPC = tc->readMiscRegNoEffect(misc_reg::TcRestart);
// TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
tc->pcState(restartPC);
@@ -171,34 +167,34 @@ template <class TC>
void
forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
{
MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(misc_reg::MvpConf0);
int num_threads = mvpConf.ptc + 1;
int success = 0;
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
TCBindReg tidTCBind =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_BIND), tid);
TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcBind), tid);
TCBindReg tcBind = tc->readMiscRegNoEffect(misc_reg::TcBind);
if (tidTCBind.curVPE == tcBind.curVPE) {
TCStatusReg tidTCStatus =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcStatus),
tid);
TCHaltReg tidTCHalt =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_HALT),
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcHalt),
tid);
if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
tidTCStatus.a == 0 && success == 0) {
setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_RESTART),
setRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcRestart),
Rs, tid);
setRegOtherThread(tc, RegId(IntRegClass, Rd_bits), Rt, tid);
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
StatusReg status = tc->readMiscReg(misc_reg::Status);
TCStatusReg tcStatus = tc->readMiscReg(misc_reg::TcStatus);
// Set Run-State to Running
tidTCStatus.rnst = 0;
@@ -214,7 +210,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
tidTCStatus.asid = tcStatus.asid;
// Write Status Register
setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
setRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcStatus),
tidTCStatus, tid);
// Mark As Successful Fork
@@ -227,9 +223,9 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
if (success == 0) {
VPEControlReg vpeControl =
tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
tc->readMiscRegNoEffect(misc_reg::VpeControl);
vpeControl.excpt = 1;
tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
tc->setMiscReg(misc_reg::VpeControl, vpeControl);
fault = std::make_shared<ThreadFault>();
}
}
@@ -240,23 +236,23 @@ int
yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
{
if (src_reg == 0) {
MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(misc_reg::MvpConf0);
ThreadID num_threads = mvpConf0.ptc + 1;
int ok = 0;
// Get Current VPE & TC numbers from calling thread
TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
TCBindReg tcBind = tc->readMiscRegNoEffect(misc_reg::TcBind);
for (ThreadID tid = 0; tid < num_threads; tid++) {
TCStatusReg tidTCStatus =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcStatus),
tid);
TCHaltReg tidTCHalt =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_HALT),
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcHalt),
tid);
TCBindReg tidTCBind =
readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_BIND),
readRegOtherThread(tc, RegId(MiscRegClass, misc_reg::TcBind),
tid);
if (tidTCBind.curVPE == tcBind.curVPE &&
@@ -269,24 +265,24 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
}
if (ok == 1) {
TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
TCStatusReg tcStatus = tc->readMiscRegNoEffect(misc_reg::TcStatus);
tcStatus.a = 0;
tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
tc->setMiscReg(misc_reg::TcStatus, tcStatus);
warn("%i: Deactivating Hardware Thread Context #%i",
curTick(), tc->threadId());
}
} else if (src_reg > 0) {
if ((src_reg & ~yield_mask) != 0) {
VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL);
VPEControlReg vpeControl = tc->readMiscReg(misc_reg::VpeControl);
vpeControl.excpt = 2;
tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
tc->setMiscReg(misc_reg::VpeControl, vpeControl);
fault = std::make_shared<ThreadFault>();
} else {
}
} else if (src_reg != -2) {
TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
TCStatusReg tcStatus = tc->readMiscRegNoEffect(misc_reg::TcStatus);
VPEControlReg vpeControl =
tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
tc->readMiscRegNoEffect(misc_reg::VpeControl);
if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
vpeControl.excpt = 4;
@@ -307,14 +303,14 @@ updateStatusView(TC *tc)
{
// TCStatus' register view must be the same as
// Status register view for CU, MX, KSU bits
TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
TCStatusReg tcStatus = tc->readMiscRegNoEffect(misc_reg::TcStatus);
StatusReg status = tc->readMiscRegNoEffect(misc_reg::Status);
status.cu = tcStatus.tcu;
status.mx = tcStatus.tmx;
status.ksu = tcStatus.tksu;
tc->setMiscRegNoEffect(MISCREG_STATUS, status);
tc->setMiscRegNoEffect(misc_reg::Status, status);
}
// TC will usually be a object derived from ThreadContext
@@ -325,14 +321,14 @@ updateTCStatusView(TC *tc)
{
// TCStatus' register view must be the same as
// Status register view for CU, MX, KSU bits
TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
TCStatusReg tcStatus = tc->readMiscRegNoEffect(misc_reg::TcStatus);
StatusReg status = tc->readMiscRegNoEffect(misc_reg::Status);
tcStatus.tcu = status.cu;
tcStatus.tmx = status.mx;
tcStatus.tksu = status.ksu;
tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
tc->setMiscRegNoEffect(misc_reg::TcStatus, tcStatus);
}
} // namespace MipsISA

6
src/arch/mips/process.cc
View File

@@ -200,9 +200,9 @@ MipsProcess::argsInit(int pageSize)
ThreadContext *tc = system->threads[contextIds[0]];
tc->setIntReg(FirstArgumentReg, argc);
tc->setIntReg(FirstArgumentReg + 1, argv_array_base);
tc->setIntReg(StackPointerReg, memState->getStackMin());
tc->setReg(int_reg::A0, argc);
tc->setReg(int_reg::A1, argv_array_base);
tc->setReg(int_reg::Sp, memState->getStackMin());
tc->pcState(getStartPC());
}

103
src/arch/mips/regs/float.hh
View File

@@ -34,28 +34,98 @@
namespace gem5
{
namespace MipsISA
{
// Constants Related to the number of registers
const int NumFloatArchRegs = 32;
const int NumFloatSpecialRegs = 5;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
namespace float_reg
{
enum FPControlRegNums
{
FLOATREG_FIR = NumFloatArchRegs,
FLOATREG_FCCR,
FLOATREG_FEXR,
FLOATREG_FENR,
FLOATREG_FCSR
_F0Idx,
_F1Idx,
_F2Idx,
_F3Idx,
_F4Idx,
_F5Idx,
_F6Idx,
_F7Idx,
_F8Idx,
_F9Idx,
_F10Idx,
_F11Idx,
_F12Idx,
_F13Idx,
_F14Idx,
_F15Idx,
_F16Idx,
_F17Idx,
_F18Idx,
_F19Idx,
_F20Idx,
_F21Idx,
_F22Idx,
_F23Idx,
_F24Idx,
_F25Idx,
_F26Idx,
_F27Idx,
_F28Idx,
_F29Idx,
_F30Idx,
_F31Idx,
NumArchRegs,
_FirIdx = NumArchRegs,
_FccrIdx,
_FexrIdx,
_FenrIdx,
_FcsrIdx,
NumRegs,
};
inline constexpr RegId
F0(FloatRegClass, _F0Idx),
F1(FloatRegClass, _F1Idx),
F2(FloatRegClass, _F2Idx),
F3(FloatRegClass, _F3Idx),
F4(FloatRegClass, _F4Idx),
F5(FloatRegClass, _F5Idx),
F6(FloatRegClass, _F6Idx),
F7(FloatRegClass, _F7Idx),
F8(FloatRegClass, _F8Idx),
F9(FloatRegClass, _F9Idx),
F10(FloatRegClass, _F10Idx),
F11(FloatRegClass, _F11Idx),
F12(FloatRegClass, _F12Idx),
F13(FloatRegClass, _F13Idx),
F14(FloatRegClass, _F14Idx),
F15(FloatRegClass, _F15Idx),
F16(FloatRegClass, _F16Idx),
F17(FloatRegClass, _F17Idx),
F18(FloatRegClass, _F18Idx),
F19(FloatRegClass, _F19Idx),
F20(FloatRegClass, _F20Idx),
F21(FloatRegClass, _F21Idx),
F22(FloatRegClass, _F22Idx),
F23(FloatRegClass, _F23Idx),
F24(FloatRegClass, _F24Idx),
F25(FloatRegClass, _F25Idx),
F26(FloatRegClass, _F26Idx),
F27(FloatRegClass, _F27Idx),
F28(FloatRegClass, _F28Idx),
F29(FloatRegClass, _F29Idx),
F30(FloatRegClass, _F30Idx),
F31(FloatRegClass, _F31Idx),
Fir(FloatRegClass, _FirIdx),
Fccr(FloatRegClass, _FccrIdx),
Fexr(FloatRegClass, _FexrIdx),
Fenr(FloatRegClass, _FenrIdx),
Fcsr(FloatRegClass, _FcsrIdx);
} // namespace float_reg
enum FCSRBits
{
Inexact = 1,
@@ -73,6 +143,9 @@ enum FCSRFields
Cause_Field = 11
};
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
} // namespace MipsISA
} // namespace gem5

180
src/arch/mips/regs/int.hh
View File

@@ -30,47 +30,175 @@
#ifndef __ARCH_MIPS_REGS_INT_HH__
#define __ARCH_MIPS_REGS_INT_HH__
#include "cpu/reg_class.hh"
namespace gem5
{
namespace MipsISA
{
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
const int NumIntSpecialRegs = 9;
const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
enum MiscIntRegNums
namespace int_reg
{
INTREG_LO = NumIntArchRegs,
INTREG_DSP_LO0 = INTREG_LO,
INTREG_HI,
INTREG_DSP_HI0 = INTREG_HI,
INTREG_DSP_ACX0,
INTREG_DSP_LO1,
INTREG_DSP_HI1,
INTREG_DSP_ACX1,
INTREG_DSP_LO2,
INTREG_DSP_HI2,
INTREG_DSP_ACX2,
INTREG_DSP_LO3,
INTREG_DSP_HI3,
INTREG_DSP_ACX3,
INTREG_DSP_CONTROL
enum : RegIndex
{
_ZeroIdx = 0,
_AtIdx = 1,
_V0Idx = 2,
_V1Idx = 3,
_A0Idx = 4,
_A1Idx = 5,
_A2Idx = 6,
_A3Idx = 7,
_T0Idx = 8,
_T1Idx = 9,
_T2Idx = 10,
_T3Idx = 11,
_T4Idx = 12,
_T5Idx = 13,
_T6Idx = 14,
_T7Idx = 15,
_S0Idx = 16,
_S1Idx = 17,
_S2Idx = 18,
_S3Idx = 19,
_S4Idx = 20,
_S5Idx = 21,
_S6Idx = 22,
_S7Idx = 23,
_T8Idx = 24,
_T9Idx = 25,
_K0Idx = 26,
_K1Idx = 27,
_GpIdx = 28,
_SpIdx = 29,
_S8Idx = 30,
_FpIdx = _S8Idx,
_RaIdx = 31,
NumArchRegs,
_LoIdx = NumArchRegs,
_DspLo0Idx = _LoIdx,
_HiIdx,
_DspHi0Idx = _HiIdx,
_DspAcx0Idx,
_DspLo1Idx,
_DspHi1Idx,
_DspAcx1Idx,
_DspLo2Idx,
_DspHi2Idx,
_DspAcx2Idx,
_DspLo3Idx,
_DspHi3Idx,
_DspAcx3Idx,
_DspControlIdx,
NumRegs
};
// semantically meaningful register indices
const int SyscallSuccessReg = 7;
const int FirstArgumentReg = 4;
const int ReturnValueReg = 2;
inline constexpr RegId
// Zero register.
Zero(IntRegClass, _ZeroIdx),
const int StackPointerReg = 29;
// Assembly temporary.
At(IntRegClass, _AtIdx),
const int SyscallPseudoReturnReg = 3;
// Value returned by subroutine.
V0(IntRegClass, _V0Idx),
V1(IntRegClass, _V1Idx),
// Arguments for subroutine.
A0(IntRegClass, _A0Idx),
A1(IntRegClass, _A1Idx),
A2(IntRegClass, _A2Idx),
A3(IntRegClass, _A3Idx),
// Temporaries.
T0(IntRegClass, _T0Idx),
T1(IntRegClass, _T1Idx),
T2(IntRegClass, _T2Idx),
T3(IntRegClass, _T3Idx),
T4(IntRegClass, _T4Idx),
T5(IntRegClass, _T5Idx),
T6(IntRegClass, _T6Idx),
T7(IntRegClass, _T7Idx),
T8(IntRegClass, _T8Idx),
T9(IntRegClass, _T9Idx),
// Subroutine registers.
S0(IntRegClass, _S0Idx),
S1(IntRegClass, _S1Idx),
S2(IntRegClass, _S2Idx),
S3(IntRegClass, _S3Idx),
S4(IntRegClass, _S4Idx),
S5(IntRegClass, _S5Idx),
S6(IntRegClass, _S6Idx),
S7(IntRegClass, _S7Idx),
// For use in an interrupt/trap handler.
K0(IntRegClass, _K0Idx),
K1(IntRegClass, _K1Idx),
// Global pointer.
Gp(IntRegClass, _GpIdx),
// Stack pointer.
Sp(IntRegClass, _SpIdx),
// Frame pointer.
Fp(IntRegClass, _FpIdx),
// Return address.
Ra(IntRegClass, _RaIdx),
DspLo0(IntRegClass, _DspLo0Idx),
DspHi0(IntRegClass, _DspHi0Idx),
DspAcx0(IntRegClass, _DspAcx0Idx),
DspLo1(IntRegClass, _DspLo1Idx),
DspHi1(IntRegClass, _DspHi1Idx),
DspAcx1(IntRegClass, _DspAcx1Idx),
DspLo2(IntRegClass, _DspLo2Idx),
DspHi2(IntRegClass, _DspHi2Idx),
DspAcx2(IntRegClass, _DspAcx2Idx),
DspLo3(IntRegClass, _DspLo3Idx),
DspHi3(IntRegClass, _DspHi3Idx),
DspAcx3(IntRegClass, _DspAcx3Idx),
DspControl(IntRegClass, _DspControlIdx);
// Register aliases.
inline constexpr auto
&S8 = Fp,
&Lo = DspLo0,
&Hi = DspHi0,
&SyscallSuccess = A3;
} // namespace int_reg
} // namespace MipsISA
} // namespace gem5

226
src/arch/mips/regs/misc.hh
View File

@@ -32,9 +32,10 @@
namespace gem5
{
namespace MipsISA
{
namespace misc_reg
{
// Enumerate names for 'Control' Registers in the CPU
// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
@@ -43,157 +44,158 @@ namespace MipsISA
// The first set of names classify the CP0 names as Register Banks
// for easy indexing when using the 'RD + SEL' index combination
// in CP0 instructions.
enum MiscRegIndex
enum : RegIndex
{
MISCREG_INDEX = 0, //Bank 0: 0 - 3
MISCREG_MVP_CONTROL,
MISCREG_MVP_CONF0,
MISCREG_MVP_CONF1,
Index = 0, //Bank 0: 0 - 3
MvpControl,
MvpConf0,
MvpConf1,
MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
MISCREG_VPE_CONTROL,
MISCREG_VPE_CONF0,
MISCREG_VPE_CONF1,
MISCREG_YQMASK,
MISCREG_VPE_SCHEDULE,
MISCREG_VPE_SCHEFBACK,
MISCREG_VPE_OPT,
Cp0Random = 8, //Bank 1: 8 - 15
VpeControl,
VpeConf0,
VpeConf1,
Yqmask,
VpeSchedule,
VpeSchefback,
VpeOpt,
MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
MISCREG_TC_STATUS,
MISCREG_TC_BIND,
MISCREG_TC_RESTART,
MISCREG_TC_HALT,
MISCREG_TC_CONTEXT,
MISCREG_TC_SCHEDULE,
MISCREG_TC_SCHEFBACK,
Entrylo0 = 16, //Bank 2: 16 - 23
TcStatus,
TcBind,
TcRestart,
TcHalt,
TcContext,
TcSchedule,
TcSchefback,
MISCREG_ENTRYLO1 = 24, // Bank 3: 24
Entrylo1 = 24, // Bank 3: 24
MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
MISCREG_CONTEXT_CONFIG,
Context = 32, // Bank 4: 32 - 33
ContextConfig,
MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
MISCREG_PAGEGRAIN = 41,
Pagemask = 40, //Bank 5: 40 - 41
Pagegrain = 41,
MISCREG_WIRED = 48, //Bank 6:48-55
MISCREG_SRS_CONF0,
MISCREG_SRS_CONF1,
MISCREG_SRS_CONF2,
MISCREG_SRS_CONF3,
MISCREG_SRS_CONF4,
Wired = 48, //Bank 6:48-55
SrsConf0,
SrsConf1,
SrsConf2,
SrsConf3,
SrsConf4,
MISCREG_HWRENA = 56, //Bank 7: 56-63
Hwrena = 56, //Bank 7: 56-63
MISCREG_BADVADDR = 64, //Bank 8: 64-71
Badvaddr = 64, //Bank 8: 64-71
MISCREG_COUNT = 72, //Bank 9: 72-79
Count = 72, //Bank 9: 72-79
MISCREG_ENTRYHI = 80, //Bank 10: 80-87
Entryhi = 80, //Bank 10: 80-87
MISCREG_COMPARE = 88, //Bank 11: 88-95
Compare = 88, //Bank 11: 88-95
MISCREG_STATUS = 96, //Bank 12: 96-103
MISCREG_INTCTL,
MISCREG_SRSCTL,
MISCREG_SRSMAP,
Status = 96, //Bank 12: 96-103
Intctl,
Srsctl,
Srsmap,
MISCREG_CAUSE = 104, //Bank 13: 104-111
Cause = 104, //Bank 13: 104-111
MISCREG_EPC = 112, //Bank 14: 112-119
Epc = 112, //Bank 14: 112-119
MISCREG_PRID = 120, //Bank 15: 120-127,
MISCREG_EBASE,
Prid = 120, //Bank 15: 120-127,
Ebase,
MISCREG_CONFIG = 128, //Bank 16: 128-135
MISCREG_CONFIG1,
MISCREG_CONFIG2,
MISCREG_CONFIG3,
MISCREG_CONFIG4,
MISCREG_CONFIG5,
MISCREG_CONFIG6,
MISCREG_CONFIG7,
Config = 128, //Bank 16: 128-135
Config1,
Config2,
Config3,
Config4,
Config5,
Config6,
Config7,
MISCREG_LLADDR = 136, //Bank 17: 136-143
Lladdr = 136, //Bank 17: 136-143
MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
MISCREG_WATCHLO1,
MISCREG_WATCHLO2,
MISCREG_WATCHLO3,
MISCREG_WATCHLO4,
MISCREG_WATCHLO5,
MISCREG_WATCHLO6,
MISCREG_WATCHLO7,
Watchlo0 = 144, //Bank 18: 144-151
Watchlo1,
Watchlo2,
Watchlo3,
Watchlo4,
Watchlo5,
Watchlo6,
Watchlo7,
MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
MISCREG_WATCHHI1,
MISCREG_WATCHHI2,
MISCREG_WATCHHI3,
MISCREG_WATCHHI4,
MISCREG_WATCHHI5,
MISCREG_WATCHHI6,
MISCREG_WATCHHI7,
Watchhi0 = 152, //Bank 19: 152-159
Watchhi1,
Watchhi2,
Watchhi3,
Watchhi4,
Watchhi5,
Watchhi6,
Watchhi7,
MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
Xccontext64 = 160, //Bank 20: 160-167
//Bank 21: 168-175
//Bank 22: 176-183
MISCREG_DEBUG = 184, //Bank 23: 184-191
MISCREG_TRACE_CONTROL1,
MISCREG_TRACE_CONTROL2,
MISCREG_USER_TRACE_DATA,
MISCREG_TRACE_BPC,
Debug = 184, //Bank 23: 184-191
TraceControl1,
TraceControl2,
UserTraceData,
TraceBpc,
MISCREG_DEPC = 192, //Bank 24: 192-199
Depc = 192, //Bank 24: 192-199
MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
MISCREG_PERFCNT1,
MISCREG_PERFCNT2,
MISCREG_PERFCNT3,
MISCREG_PERFCNT4,
MISCREG_PERFCNT5,
MISCREG_PERFCNT6,
MISCREG_PERFCNT7,
Perfcnt0 = 200, //Bank 25: 200-207
Perfcnt1,
Perfcnt2,
Perfcnt3,
Perfcnt4,
Perfcnt5,
Perfcnt6,
Perfcnt7,
MISCREG_ERRCTL = 208, //Bank 26: 208-215
Errctl = 208, //Bank 26: 208-215
MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
MISCREG_CACHEERR1,
MISCREG_CACHEERR2,
MISCREG_CACHEERR3,
Cacheerr0 = 216, //Bank 27: 216-223
Cacheerr1,
Cacheerr2,
Cacheerr3,
MISCREG_TAGLO0 = 224, //Bank 28: 224-231
MISCREG_DATALO1,
MISCREG_TAGLO2,
MISCREG_DATALO3,
MISCREG_TAGLO4,
MISCREG_DATALO5,
MISCREG_TAGLO6,
MISCREG_DATALO7,
Taglo0 = 224, //Bank 28: 224-231
Datalo1,
Taglo2,
Datalo3,
Taglo4,
Datalo5,
Taglo6,
Datalo7,
MISCREG_TAGHI0 = 232, //Bank 29: 232-239
MISCREG_DATAHI1,
MISCREG_TAGHI2,
MISCREG_DATAHI3,
MISCREG_TAGHI4,
MISCREG_DATAHI5,
MISCREG_TAGHI6,
MISCREG_DATAHI7,
Taghi0 = 232, //Bank 29: 232-239
Datahi1,
Taghi2,
Datahi3,
Taghi4,
Datahi5,
Taghi6,
Datahi7,
MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
ErrorEpc = 240, //Bank 30: 240-247
MISCREG_DESAVE = 248, //Bank 31: 248-256
Desave = 248, //Bank 31: 248-256
MISCREG_LLFLAG = 257,
MISCREG_TP_VALUE,
Llflag = 257,
TpValue,
MISCREG_NUMREGS
NumRegs
};
} // namespace misc_reg
} // namespace MipsISA
} // namespace gem5

40
src/arch/mips/remote_gdb.cc
View File

@@ -173,16 +173,18 @@ RemoteGDB::MipsGdbRegCache::getRegs(ThreadContext *context)
{
DPRINTF(GDBAcc, "getregs in remotegdb \n");
for (int i = 0; i < 32; i++) r.gpr[i] = context->readIntReg(i);
r.sr = context->readMiscRegNoEffect(MISCREG_STATUS);
r.lo = context->readIntReg(INTREG_LO);
r.hi = context->readIntReg(INTREG_HI);
r.badvaddr = context->readMiscRegNoEffect(MISCREG_BADVADDR);
r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE);
for (int i = 0; i < 32; i++)
r.gpr[i] = context->getReg(RegId(IntRegClass, i));
r.sr = context->readMiscRegNoEffect(misc_reg::Status);
r.lo = context->getReg(int_reg::Lo);
r.hi = context->getReg(int_reg::Hi);
r.badvaddr = context->readMiscRegNoEffect(misc_reg::Badvaddr);
r.cause = context->readMiscRegNoEffect(misc_reg::Cause);
r.pc = context->pcState().instAddr();
for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatReg(i);
r.fsr = context->readFloatReg(FLOATREG_FCCR);
r.fir = context->readFloatReg(FLOATREG_FIR);
for (int i = 0; i < 32; i++)
r.fpr[i] = context->getReg(RegId(FloatRegClass, i));
r.fsr = context->getReg(float_reg::Fccr);
r.fir = context->getReg(float_reg::Fir);
}
void
@@ -190,16 +192,18 @@ RemoteGDB::MipsGdbRegCache::setRegs(ThreadContext *context) const
{
DPRINTF(GDBAcc, "setregs in remotegdb \n");
for (int i = 1; i < 32; i++) context->setIntReg(i, r.gpr[i]);
context->setMiscRegNoEffect(MISCREG_STATUS, r.sr);
context->setIntReg(INTREG_LO, r.lo);
context->setIntReg(INTREG_HI, r.hi);
context->setMiscRegNoEffect(MISCREG_BADVADDR, r.badvaddr);
context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause);
for (int i = 1; i < 32; i++)
context->setReg(RegId(IntRegClass, i), r.gpr[i]);
context->setMiscRegNoEffect(misc_reg::Status, r.sr);
context->setReg(int_reg::Lo, r.lo);
context->setReg(int_reg::Hi, r.hi);
context->setMiscRegNoEffect(misc_reg::Badvaddr, r.badvaddr);
context->setMiscRegNoEffect(misc_reg::Cause, r.cause);
context->pcState(r.pc);
for (int i = 0; i < 32; i++) context->setFloatReg(i, r.fpr[i]);
context->setFloatReg(FLOATREG_FCCR, r.fsr);
context->setFloatReg(FLOATREG_FIR, r.fir);
for (int i = 0; i < 32; i++)
context->setReg(RegId(FloatRegClass, i), r.fpr[i]);
context->setReg(float_reg::Fccr, r.fsr);
context->setReg(float_reg::Fir, r.fir);
}
BaseGdbRegCache*

10
src/arch/mips/se_workload.hh
View File

@@ -79,15 +79,15 @@ struct Result<MipsISA::SEWorkload::SyscallABI, SyscallReturn>
{
if (ret.successful()) {
// no error
tc->setIntReg(MipsISA::SyscallSuccessReg, 0);
tc->setIntReg(MipsISA::ReturnValueReg, ret.returnValue());
tc->setReg(MipsISA::int_reg::SyscallSuccess, (RegVal)0);
tc->setReg(MipsISA::int_reg::V0, ret.returnValue());
} else {
// got an error, return details
tc->setIntReg(MipsISA::SyscallSuccessReg, (uint32_t)(-1));
tc->setIntReg(MipsISA::ReturnValueReg, ret.errnoValue());
tc->setReg(MipsISA::int_reg::SyscallSuccess, (uint32_t)(-1));
tc->setReg(MipsISA::int_reg::V0, ret.errnoValue());
}
if (ret.count() > 1)
tc->setIntReg(MipsISA::SyscallPseudoReturnReg, ret.value2());
tc->setReg(MipsISA::int_reg::V1, ret.value2());
}
};