Gabe Black 84ae0afa59 arch-x86: Put misc reg indexes into a name space. ...

Also make them match the style guide.

Change-Id: I845f141f85d4499a5acf56c2161240764906a232
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49758
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>

2022-06-08 07:09:05 +00:00

..

amdgpu

arch-x86: Put misc reg indexes into a name space.

2022-06-08 07:09:05 +00:00

arm

arch: Remove plumbing for an op_idx value in ISA operands.

2022-06-08 07:07:35 +00:00

generic

arch: Add an "as" template to dummy vec regs.

2022-03-16 15:02:44 +00:00

isa_parser

arch: Remove plumbing for an op_idx value in ISA operands.

2022-06-08 07:07:35 +00:00

mips

arch,cpu: Remove the idea of a zero register.

2022-06-07 18:26:33 +00:00

null

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

power

arch,cpu: Remove the idea of a zero register.

2022-06-07 18:26:33 +00:00

riscv

arch,cpu: Remove the idea of a zero register.

2022-06-07 18:26:33 +00:00

sparc

arch,cpu: Remove the idea of a zero register.

2022-06-07 18:26:33 +00:00

x86

arch-x86: Put misc reg indexes into a name space.

2022-06-08 07:09:05 +00:00

micro_asm_test.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

micro_asm.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

SConscript

scons: Put all config variables in an env['CONF'] sub-dict.

2022-03-28 20:31:21 +00:00

SConsopts

scons: Make all sticky variables automatically exported.

2022-03-15 00:45:30 +00:00