arch: Remove TheISA::VecElem from arch/vecregs.hh.

Also remove unnecessary includes from the x86 version, and fix up
transitive includes from other x86 files.

Change-Id: I9f7d330f287c9ed52eed1544c47251b4354cfab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49166
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/generic/vec_reg.hh

@@ -263,8 +263,7 @@ struct ShowParam<VecRegContainer<Sz>>
  * vector registers.
  */
 /** @{ */
-using DummyVecElem = uint32_t;
-using DummyVecRegContainer = VecRegContainer<2 * sizeof(DummyVecElem)>;
+using DummyVecRegContainer = VecRegContainer<8>;
 /** @} */
 
 } // namespace gem5

src/arch/mips/vecregs.hh

@@ -40,10 +40,7 @@ namespace MipsISA
 {
 
 // Not applicable to MIPS
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to MIPS
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace MipsISA

src/arch/null/vecregs.hh

@@ -38,8 +38,6 @@
 #ifndef __ARCH_NULL_VECREGS_HH__
 #define __ARCH_NULL_VECREGS_HH__
 
-#include <cstdint>
-
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 
@@ -50,10 +48,7 @@ namespace NullISA
 {
 
 // Not applicable to null
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to null
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace NullISA

src/arch/power/vecregs.hh

@@ -30,8 +30,6 @@
 #ifndef __ARCH_POWER_VECREGS_HH__
 #define __ARCH_POWER_VECREGS_HH__
 
-#include <cstdint>
-
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 
@@ -42,10 +40,7 @@ namespace PowerISA
 {
 
 // Not applicable to Power
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to Power
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace PowerISA

src/arch/riscv/vecregs.hh

@@ -46,8 +46,6 @@
 #ifndef __ARCH_RISCV_VECREGS_HH__
 #define __ARCH_RISCV_VECREGS_HH__
 
-#include <cstdint>
-
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 
@@ -58,10 +56,7 @@ namespace RiscvISA
 {
 
 // Not applicable to RISC-V
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to RISC-V
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace RiscvISA

src/arch/sparc/vecregs.hh

@@ -39,10 +39,7 @@ namespace SparcISA
 {
 
 // Not applicable to SPARC
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to SPARC
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace SparcISA

src/arch/x86/faults.cc

@@ -43,6 +43,7 @@
 #include "arch/x86/generated/decoder.hh"
 #include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/mmu.hh"
+#include "arch/x86/regs/misc.hh"
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"

src/arch/x86/interrupts.cc

@@ -54,6 +54,7 @@
 
 #include "arch/x86/intmessage.hh"
 #include "arch/x86/regs/apic.hh"
+#include "arch/x86/regs/misc.hh"
 #include "cpu/base.hh"
 #include "debug/LocalApic.hh"
 #include "dev/x86/i82094aa.hh"

src/arch/x86/isa/includes.isa

@@ -62,6 +62,9 @@ output header {{
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/microspecop.hh"
 #include "arch/x86/insts/static_inst.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/utility.hh"
 #include "base/logging.hh"
@@ -81,6 +84,7 @@ output decoder {{
 #include "arch/x86/decoder.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/microcode_rom.hh"
+#include "arch/x86/regs/ccr.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/misc.hh"

src/arch/x86/linux/linux.hh

@@ -40,6 +40,8 @@
 
 #include <map>
 
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/utility.hh"
 #include "base/compiler.hh"
 #include "kern/linux/flag_tables.hh"

src/arch/x86/linux/se_workload.cc

@@ -44,6 +44,7 @@
 #include "arch/x86/page_size.hh"
 #include "arch/x86/process.hh"
 #include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/se_workload.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"

src/arch/x86/linux/se_workload.hh

@@ -40,6 +40,7 @@
 #define __ARCH_X86_LINUX_SE_WORKLOAD_HH__
 
 #include "arch/x86/linux/linux.hh"
+#include "arch/x86/regs/int.hh"
 #include "arch/x86/remote_gdb.hh"
 #include "params/X86EmuLinux.hh"
 #include "sim/process.hh"

src/arch/x86/pagetable_walker.cc

@@ -53,6 +53,7 @@
 
 #include "arch/x86/faults.hh"
 #include "arch/x86/pagetable.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/tlb.hh"
 #include "base/bitfield.hh"
 #include "base/trie.hh"

src/arch/x86/process.cc

@@ -46,6 +46,7 @@
 
 #include "arch/x86/fs_workload.hh"
 #include "arch/x86/page_size.hh"
+#include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/se_workload.hh"

src/arch/x86/vecregs.hh

@@ -41,10 +41,6 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/x86/regs/ccr.hh"
-#include "arch/x86/regs/float.hh"
-#include "arch/x86/regs/int.hh"
-#include "arch/x86/regs/misc.hh"
 
 namespace gem5
 {
@@ -53,10 +49,7 @@ namespace X86ISA
 {
 
 // Not applicable to x86
-using VecElem = ::gem5::DummyVecElem;
 using VecRegContainer = ::gem5::DummyVecRegContainer;
-
-// Not applicable to x86
 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
 } // namespace X86ISA