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arch: Switch the generic register ABI over to use RegId.

Browse Source 
Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49774
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-08-29 00:16:52 -07:00
parent 644ab97727
commit 6a73a3a2d0
13 changed files with 34 additions and 22 deletions
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11
src/arch/arm/reg_abi.cc
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@@ -26,6 +26,7 @@
*/
#include "arch/arm/reg_abi.hh"
#include "arch/arm/regs/int.hh"
namespace gem5
{
@@ -33,8 +34,14 @@ namespace gem5
namespace ArmISA
{
const std::vector<int> RegABI32::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6};
const std::vector<int> RegABI64::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6};
const std::vector<RegId> RegABI32::ArgumentRegs = {
int_reg::R0, int_reg::R1, int_reg::R2, int_reg::R3,
int_reg::R4, int_reg::R5, int_reg::R6
};
const std::vector<RegId> RegABI64::ArgumentRegs = {
int_reg::X0, int_reg::X1, int_reg::X2, int_reg::X3,
int_reg::X4, int_reg::X5, int_reg::X6
};
} // namespace ArmISA
} // namespace gem5

4
src/arch/arm/reg_abi.hh
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@@ -41,12 +41,12 @@ namespace ArmISA
struct RegABI32 : public GenericSyscallABI32
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
struct RegABI64 : public GenericSyscallABI64
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
} // namespace ArmISA

5
src/arch/mips/se_workload.cc
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@@ -33,8 +33,9 @@ namespace gem5
namespace MipsISA
{
const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
4, 5, 6, 7, 8, 9
const std::vector<RegId> SEWorkload::SyscallABI::ArgumentRegs = {
int_reg::A0, int_reg::A1, int_reg::A2,
int_reg::A3, int_reg::T0, int_reg::T1
};
} // namespace MipsISA

2
src/arch/mips/se_workload.hh
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@@ -61,7 +61,7 @@ class SEWorkload : public gem5::SEWorkload
struct SyscallABI : public GenericSyscallABI64
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
};

2
src/arch/power/se_workload.cc
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@@ -33,7 +33,7 @@ namespace gem5
namespace PowerISA
{
const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
const std::vector<RegId> SEWorkload::SyscallABI::ArgumentRegs = {
ArgumentReg0,
ArgumentReg1,
ArgumentReg2,

2
src/arch/power/se_workload.hh
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@@ -61,7 +61,7 @@ class SEWorkload : public gem5::SEWorkload
struct SyscallABI : public GenericSyscallABI64
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
};

6
src/arch/riscv/reg_abi.cc
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@@ -26,6 +26,7 @@
*/
#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/regs/int.hh"
namespace gem5
{
@@ -33,7 +34,10 @@ namespace gem5
namespace RiscvISA
{
const std::vector<int> RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
const std::vector<RegId> RegABI64::ArgumentRegs = {
int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
int_reg::A4, int_reg::A5, int_reg::A6
};
} // namespace RiscvISA
} // namespace gem5

2
src/arch/riscv/reg_abi.hh
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@@ -41,7 +41,7 @@ namespace RiscvISA
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
struct RegABI64 : public GenericSyscallABI64
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
} // namespace RiscvISA

2
src/arch/sparc/se_workload.cc
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@@ -41,7 +41,7 @@ namespace gem5
namespace SparcISA
{
const std::vector<int> SEWorkload::BaseSyscallABI::ArgumentRegs = {
const std::vector<RegId> SEWorkload::BaseSyscallABI::ArgumentRegs = {
int_reg::O0, int_reg::O1, int_reg::O2,
int_reg::O3, int_reg::O4, int_reg::O5
};

2
src/arch/sparc/se_workload.hh
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@@ -63,7 +63,7 @@ class SEWorkload : public gem5::SEWorkload
struct BaseSyscallABI
{
static const std::vector<int> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
struct SyscallABI32 : public GenericSyscallABI32,

4
src/arch/x86/linux/se_workload.cc
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@@ -97,12 +97,12 @@ namespace X86ISA
EmuLinux::EmuLinux(const Params &p) : SEWorkload(p, PageShift)
{}
const std::vector<RegIndex> EmuLinux::SyscallABI64::ArgumentRegs = {
const std::vector<RegId> EmuLinux::SyscallABI64::ArgumentRegs = {
int_reg::Rdi, int_reg::Rsi, int_reg::Rdx,
int_reg::R10, int_reg::R8, int_reg::R9
};
const std::vector<RegIndex> EmuLinux::SyscallABI32::ArgumentRegs = {
const std::vector<RegId> EmuLinux::SyscallABI32::ArgumentRegs = {
int_reg::Ebx, int_reg::Ecx, int_reg::Edx,
int_reg::Esi, int_reg::Edi, int_reg::Ebp
};

4
src/arch/x86/linux/se_workload.hh
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@@ -79,13 +79,13 @@ class EmuLinux : public SEWorkload
struct SyscallABI64 :
public GenericSyscallABI64, public X86Linux::SyscallABI
{
static const std::vector<RegIndex> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
struct SyscallABI32 :
public GenericSyscallABI32, public X86Linux::SyscallABI
{
static const std::vector<RegIndex> ArgumentRegs;
static const std::vector<RegId> ArgumentRegs;
};
private:

10
src/sim/syscall_abi.hh
View File

@@ -67,10 +67,10 @@ struct GenericSyscallABI32 : public GenericSyscallABI
// Read two registers and merge them into one value.
static uint64_t
mergeRegs(ThreadContext *tc, RegIndex low_idx, RegIndex high_idx)
mergeRegs(ThreadContext *tc, const RegId &low_id, const RegId &high_id)
{
RegVal low = tc->readIntReg(low_idx);
RegVal high = tc->readIntReg(high_idx);
RegVal low = tc->getReg(low_id);
RegVal high = tc->getReg(high_id);
return insertBits(low, 63, 32, high);
}
};
@@ -91,7 +91,7 @@ struct Argument<ABI, Arg,
{
panic_if(state >= ABI::ArgumentRegs.size(),
"Ran out of syscall argument registers.");
return tc->readIntReg(ABI::ArgumentRegs[state++]);
return tc->getReg(ABI::ArgumentRegs[state++]);
}
};
@@ -107,7 +107,7 @@ struct Argument<ABI, Arg,
{
panic_if(state >= ABI::ArgumentRegs.size(),
"Ran out of syscall argument registers.");
return bits(tc->readIntReg(ABI::ArgumentRegs[state++]), 31, 0);
return bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
}
};