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arch-sparc: Revamp the float registers.

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Change-Id: Iec52e15f1529319345795496a82a37e1f0aeebae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49769
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-08-28 22:36:38 -07:00
parent 0de5b1f173
commit 644ab97727
2 changed files with 10 additions and 5 deletions
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7
src/arch/sparc/isa.cc
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@@ -71,7 +71,7 @@ static const PSTATE PstateMask = buildPstateMask();
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
@@ -253,8 +253,9 @@ ISA::copyRegsFrom(ThreadContext *src)
// Then loop through the floating point registers.
for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
tc->setFloatReg(i, src->readFloatReg(i));
for (int i = 0; i < SparcISA::float_reg::NumArchRegs; ++i) {
RegId reg(FloatRegClass, i);
tc->setReg(reg, src->getReg(reg));
}
// Copy misc. registers

8
src/arch/sparc/regs/float.hh
View File

@@ -35,9 +35,13 @@ namespace gem5
namespace SparcISA
{
const int NumFloatRegs = 64;
const int NumFloatArchRegs = NumFloatRegs;
namespace float_reg
{
const int NumRegs = 64;
const int NumArchRegs = NumRegs;
} // namespace float_reg
} // namespace SparcISA
} // namespace gem5