diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 279bd1a03f..c1fd39932f 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -71,7 +71,7 @@ static const PSTATE PstateMask = buildPstateMask();
 ISA::ISA(const Params &p) : BaseISA(p)
 {
     _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
-    _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
+    _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
     _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
     _regClasses.emplace_back(2, debug::IntRegs); // Not applicable for SPARC
     _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
@@ -253,8 +253,9 @@ ISA::copyRegsFrom(ThreadContext *src)
 
 
     // Then loop through the floating point registers.
-    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
-        tc->setFloatReg(i, src->readFloatReg(i));
+    for (int i = 0; i < SparcISA::float_reg::NumArchRegs; ++i) {
+        RegId reg(FloatRegClass, i);
+        tc->setReg(reg, src->getReg(reg));
     }
 
     // Copy misc. registers
diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh
index 3588090029..78f4db5f74 100644
--- a/src/arch/sparc/regs/float.hh
+++ b/src/arch/sparc/regs/float.hh
@@ -35,9 +35,13 @@ namespace gem5
 namespace SparcISA
 {
 
-const int NumFloatRegs = 64;
-const int NumFloatArchRegs = NumFloatRegs;
+namespace float_reg
+{
 
+const int NumRegs = 64;
+const int NumArchRegs = NumRegs;
+
+} // namespace float_reg
 } // namespace SparcISA
 } // namespace gem5