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arch-arm: Do not trap SIMD insts to EL1 if in VHE host

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Change-Id: I4ea326eead1aec1e013280b599c57f2202901625
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60971
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-06-28 14:21:11 +01:00
parent 343f7b7bf6
commit ccdec1b11d
1 changed files with 4 additions and 3 deletions
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7
src/arch/arm/insts/static_inst.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2014, 2016-2020 ARM Limited
* Copyright (c) 2010-2014, 2016-2020,2022 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -715,8 +715,9 @@ ArmStaticInst::checkFPAdvSIMDEnabled64(ThreadContext *tc,
CPSR cpsr, CPACR cpacr) const
{
const ExceptionLevel el = currEL(tc);
if ((el == EL0 && cpacr.fpen != 0x3) ||
(el == EL1 && !(cpacr.fpen & 0x1)))
if (((el == EL0 && cpacr.fpen != 0x3) ||
(el == EL1 && !(cpacr.fpen & 0x1))) &&
!ELIsInHost(tc, el))
return advSIMDFPAccessTrap64(EL1);
return checkFPAdvSIMDTrap64(tc, cpsr);