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arch-arm: Do not trap MISCREG_DC_ZVA_Xt to EL1 if in VHE host

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Change-Id: I785be01fcb97b78e0b59f8f9a4f8d150208fa88a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60970
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-06-28 14:20:49 +01:00
parent ea9620922c
commit 343f7b7bf6
1 changed files with 3 additions and 2 deletions
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5
src/arch/arm/insts/misc64.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2013,2017-2021 Arm Limited
* Copyright (c) 2011-2013,2017-2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -135,7 +135,8 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
case MISCREG_DC_ZVA_Xt:
// In syscall-emulation mode, this test is skipped and DCZVA is always
// allowed at EL0
trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
trap_to_sup = el == EL0 && !(EL2Enabled(tc) && hcr.e2h && hcr.tge) &&
!sctlr.dze && FullSystem;
break;
case MISCREG_DC_CIVAC_Xt:
case MISCREG_DC_CVAC_Xt: