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arch,cpu: Keep track of the RegClassType of a RegClass.

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This makes it possible to do more things with a RegClass locally.

Change-Id: Ib7d7fa3e2d88a34d5b5681fcc4aab26696c71205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49779
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-08-30 03:18:50 -07:00
parent 4c55722ccd
commit 85a18e22a1
7 changed files with 75 additions and 51 deletions
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23
src/arch/arm/isa.cc
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@@ -92,16 +92,19 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(0, debug::FloatRegs);
_regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
sizeof(VecRegContainer));
_regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
vecRegElemClassOps, debug::VecRegs);
_regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps,
debug::VecPredRegs, sizeof(VecPredRegContainer));
_regClasses.emplace_back(cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, 0, debug::FloatRegs);
_regClasses.emplace_back(VecRegClass, NumVecRegs, vecRegClassOps,
debug::VecRegs, sizeof(VecRegContainer));
_regClasses.emplace_back(VecElemClass,
NumVecRegs * ArmISA::NumVecElemPerVecReg, vecRegElemClassOps,
debug::VecRegs);
_regClasses.emplace_back(VecPredRegClass, NumVecPredRegs,
vecPredRegClassOps, debug::VecPredRegs,
sizeof(VecPredRegContainer));
_regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, miscRegClassOps,
debug::MiscRegs);
miscRegs[MISCREG_SCTLR_RST] = 0;

18
src/arch/mips/isa.cc
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@@ -100,13 +100,17 @@ ISA::miscRegNames[misc_reg::NumRegs] =
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(0, debug::IntRegs); // Not applicable to MIPS.
_regClasses.emplace_back(misc_reg::NumRegs, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to MIPS. */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs, debug::MiscRegs);
miscRegFile.resize(misc_reg::NumRegs);
bankType.resize(misc_reg::NumRegs);

15
src/arch/power/isa.cc
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@@ -54,13 +54,14 @@ namespace PowerISA
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs);
_regClasses.emplace_back(2, debug::IntRegs);
_regClasses.emplace_back(1, debug::IntRegs);
_regClasses.emplace_back(0, debug::IntRegs);
_regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
clear();
}

18
src/arch/riscv/isa.cc
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@@ -196,13 +196,17 @@ namespace RiscvISA
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(0, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to RISCV */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
miscRegFile.resize(NUM_MISCREGS);
clear();

18
src/arch/sparc/isa.cc
View File

@@ -70,13 +70,17 @@ static const PSTATE PstateMask = buildPstateMask();
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(0, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(NumMiscRegs, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable for SPARC */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
_regClasses.emplace_back(MiscRegClass, NumMiscRegs, debug::MiscRegs);
clear();
}

18
src/arch/x86/isa.cc
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@@ -146,13 +146,17 @@ ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to X86
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to X86
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to X86
_regClasses.emplace_back(cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(misc_reg::NumRegs, debug::MiscRegs);
_regClasses.emplace_back(IntRegClass, int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
/* Not applicable to X86 */
_regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
_regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
_regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
_regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs, debug::MiscRegs);
clear();
}

16
src/cpu/reg_class.hh
View File

@@ -81,6 +81,8 @@ class RegClassOps
class RegClass
{
private:
RegClassType _type;
size_t _numRegs;
size_t _regBytes;
// This is how much to shift an index by to get an offset of a register in
@@ -93,18 +95,20 @@ class RegClass
const debug::Flag &debugFlag;
public:
constexpr RegClass(size_t num_regs, const debug::Flag &debug_flag,
size_t reg_bytes=sizeof(RegVal)) :
_numRegs(num_regs), _regBytes(reg_bytes),
constexpr RegClass(RegClassType type, size_t num_regs,
const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal)) :
_type(type), _numRegs(num_regs), _regBytes(reg_bytes),
_regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
{}
constexpr RegClass(size_t num_regs, RegClassOps &new_ops,
const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal)) :
RegClass(num_regs, debug_flag, reg_bytes)
constexpr RegClass(RegClassType type, size_t num_regs,
RegClassOps &new_ops, const debug::Flag &debug_flag,
size_t reg_bytes=sizeof(RegVal)) :
RegClass(type, num_regs, debug_flag, reg_bytes)
{
_ops = &new_ops;
}
constexpr RegClassType type() const { return _type; }
constexpr size_t numRegs() const { return _numRegs; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }