arch-riscv: Treat InvalidRegClass as zero register.

Currently the disassembler will print the zero register as ft0, this commit provides a workaround to solve this problem.

Change-Id: Ic8ac3f277dd9ff886dc84a83c022954ad30c47f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61150
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/utility.hh

@@ -122,13 +122,18 @@ registerName(RegId reg)
             return str.str();
         }
         return int_reg::RegNames[reg.index()];
-    } else {
+    } else if (reg.is(FloatRegClass)) {
         if (reg.index() >= float_reg::NumRegs) {
             std::stringstream str;
             str << "?? (f" << reg.index() << ')';
             return str.str();
         }
         return float_reg::RegNames[reg.index()];
+    } else {
+        /* It must be an InvalidRegClass, in RISC-V we should treat it as a
+         * zero register for the disassembler to work correctly.
+         */
+        return int_reg::RegNames[reg.index()];
     }
 }