From f5d15871f381b67d6fe498f95ed153c69aed52c5 Mon Sep 17 00:00:00 2001 From: ksco Date: Fri, 8 Jul 2022 00:56:16 +0800 Subject: [PATCH] arch-riscv: Treat InvalidRegClass as zero register. Currently the disassembler will print the zero register as ft0, this commit provides a workaround to solve this problem. Change-Id: Ic8ac3f277dd9ff886dc84a83c022954ad30c47f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61150 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/utility.hh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 93d6b517b7..3bd34c4801 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -122,13 +122,18 @@ registerName(RegId reg) return str.str(); } return int_reg::RegNames[reg.index()]; - } else { + } else if (reg.is(FloatRegClass)) { if (reg.index() >= float_reg::NumRegs) { std::stringstream str; str << "?? (f" << reg.index() << ')'; return str.str(); } return float_reg::RegNames[reg.index()]; + } else { + /* It must be an InvalidRegClass, in RISC-V we should treat it as a + * zero register for the disassembler to work correctly. + */ + return int_reg::RegNames[reg.index()]; } }