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cpu: x86: add serialize and fence instructions to the isa

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Clarify commented out lines.

Issue-On: https://gem5.atlassian.net/browse/GEM5-1231

Change-Id: I15d685ca233b56e0aece312bc85a9bff0d56e4dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60929
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Eliot Moss
2022-07-02 13:23:32 -04:00
committed by Eliot Moss
parent f6082ba24b
commit 23b2561bf6
2 changed files with 99 additions and 2 deletions
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8
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View File

@@ -133,7 +133,13 @@
0x3: Inst::SMSW(Rv);
default: Inst::SMSW(Mw);
}
0x6: Cpl0Inst::LMSW(Ew);
0x5: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: BasicOperate::SERIALIZE({{/*Nothing*/}},
IsSerializeAfter);
}
}
0x6: Inst::LMSW(Ew);
0x7: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: Cpl0Inst::SWAPGS();

93
src/arch/x86/isa/microops/specop.isa
View File

@@ -134,7 +134,7 @@ let {{
}};
def template MicroFenceOpDeclare {{
class %(class_name)s : public X86ISA::X86MicroopBase
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
@@ -190,4 +190,95 @@ let {{
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
# exec_output += BasicExecute.subst(iop)
}};
let {{
class SfenceOp(X86Microop):
def __init__(self):
self.className = "Sfence"
self.mnemonic = "sfence"
self.instFlags = "| (1ULL << StaticInst::IsWriteBarrier)"
def getAllocator(self, microFlags):
allocString = '''
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s))
'''
allocator = allocString % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
"flags" : self.microFlagsText(microFlags) + self.instFlags}
return allocator
microopClasses["sfence"] = SfenceOp
}};
let {{
# Build up the all register version of this micro op
iop = InstObjParams("sfence", "Sfence", 'X86MicroopBase',
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
# exec_output += BasicExecute.subst(iop)
}};
let {{
class LfenceOp(X86Microop):
def __init__(self):
self.className = "Lfence"
self.mnemonic = "lfence"
self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)"
def getAllocator(self, microFlags):
allocString = '''
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s))
'''
allocator = allocString % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
"flags" : self.microFlagsText(microFlags) + self.instFlags}
return allocator
microopClasses["lfence"] = LfenceOp
}};
let {{
# Build up the all register version of this micro op
iop = InstObjParams("lfence", "Lfence", 'X86MicroopBase',
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
# exec_output += BasicExecute.subst(iop)
}};
let {{
class SerializeOp(X86Microop):
def __init__(self):
self.className = "Serialize"
self.mnemonic = "serialize"
self.instFlags = "| (1ULL << StaticInst::IsSerializeAfter)"
def getAllocator(self, microFlags):
allocString = '''
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s))
'''
allocator = allocString % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
"flags" : self.microFlagsText(microFlags) + self.instFlags}
return allocator
microopClasses["serialize"] = SerializeOp
}};
let {{
# Build up the all register version of this micro op
iop = InstObjParams("serialize", "Serialize", 'X86MicroopBase',
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
# exec_output += BasicExecute.subst(iop)
}};