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arch-arm: Add a getter for miscRead member variable

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In this way our ISA code can check if a MiscRegOp64 is a MSR or a MRS
and act accordingly

Change-Id: I9ddb9df432b28ce7d20235fc51f3637c41f3256a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61672
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-14 11:02:01 +01:00
parent 07b6f4261c
commit e4ab0bb5cf
2 changed files with 6 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/insts/misc64.cc
View File

@@ -247,7 +247,7 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
case MISCREG_AMAIR_EL1:
case MISCREG_CONTEXTIDR_EL1:
{
bool tvm = miscRead? hcr.trvm: hcr.tvm;
bool tvm = _miscRead? hcr.trvm: hcr.tvm;
trap_to_hyp = EL2Enabled(tc) && (el == EL1) && tvm;
}
break;
@@ -804,7 +804,7 @@ MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
uint32_t
MiscRegOp64::_iss(const MiscRegNum64 &misc_reg, RegIndex int_index) const
{
return miscRead |
return _miscRead |
(misc_reg.crm << 1) |
(int_index << 5) |
(misc_reg.crn << 10) |

6
src/arch/arm/insts/misc64.hh
View File

@@ -124,12 +124,12 @@ class UnknownOp64 : public ArmISA::ArmStaticInst
class MiscRegOp64 : public ArmISA::ArmStaticInst
{
protected:
bool miscRead;
bool _miscRead;
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
OpClass __opClass, bool misc_read) :
ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
miscRead(misc_read)
_miscRead(misc_read)
{}
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg,
@@ -153,6 +153,8 @@ class MiscRegOp64 : public ArmISA::ArmStaticInst
public:
virtual uint32_t iss() const { return 0; }
bool miscRead() const { return _miscRead; }
};
class MiscRegImmOp64 : public MiscRegOp64