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arch-riscv: Revamp int regs.

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Change-Id: Ie4773178843757acede4fe9e77ca327f7b024270
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49772
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-08-28 23:45:12 -07:00
parent 6a73a3a2d0
commit 0fa9bc0780
11 changed files with 93 additions and 33 deletions
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8
src/arch/riscv/isa.cc
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@@ -196,7 +196,7 @@ namespace RiscvISA
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(NumIntRegs, debug::IntRegs);
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
@@ -217,8 +217,10 @@ void
ISA::copyRegsFrom(ThreadContext *src)
{
// First loop through the integer registers.
for (int i = 0; i < NumIntRegs; ++i)
tc->setIntReg(i, src->readIntReg(i));
for (int i = 0; i < int_reg::NumRegs; ++i) {
RegId reg(IntRegClass, i);
tc->setReg(reg, src->getReg(reg));
}
// Second loop through the float registers.
for (int i = 0; i < NumFloatRegs; ++i)

3
src/arch/riscv/isa/formats/standard.isa
View File

@@ -299,8 +299,7 @@ def template JumpExecute {{
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCStateBase *pc_ptr = tc->pcState().clone();
pc_ptr->as<PCState>().set(
(tc->readIntReg(srcRegIdx(0).index()) + imm) & ~0x1);
pc_ptr->as<PCState>().set((tc->getReg(srcRegIdx(0)) + imm) & ~0x1);
return std::unique_ptr<PCStateBase>{pc_ptr};
}

2
src/arch/riscv/linux/fs_workload.cc
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@@ -63,7 +63,7 @@ FsLinux::initState()
delete dtb_file;
for (auto *tc: system->threads) {
tc->setIntReg(11, params().dtb_addr);
tc->setReg(int_reg::A1, params().dtb_addr);
}
} else {
warn("No DTB file specified\n");

6
src/arch/riscv/linux/linux.hh
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@@ -203,9 +203,9 @@ class RiscvLinux64 : public RiscvLinux, public OpenFlagTable<RiscvLinux64>
{
ctc->getIsaPtr()->copyRegsFrom(ptc);
if (flags & TGT_CLONE_SETTLS)
ctc->setIntReg(RiscvISA::ThreadPointerReg, tls);
ctc->setReg(RiscvISA::ThreadPointerReg, tls);
if (stack)
ctc->setIntReg(RiscvISA::StackPointerReg, stack);
ctc->setReg(RiscvISA::StackPointerReg, stack);
}
};
@@ -372,7 +372,7 @@ class RiscvLinux32 : public RiscvLinux, public OpenFlagTable<RiscvLinux32>
{
ctc->getIsaPtr()->copyRegsFrom(ptc);
if (stack)
ctc->setIntReg(RiscvISA::StackPointerReg, stack);
ctc->setReg(RiscvISA::StackPointerReg, stack);
}
};

2
src/arch/riscv/linux/se_workload.cc
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@@ -86,7 +86,7 @@ EmuLinux::syscall(ThreadContext *tc)
// This will move into the base SEWorkload function at some point.
process->Process::syscall(tc);
RegVal num = tc->readIntReg(RiscvISA::SyscallNumReg);
RegVal num = tc->getReg(RiscvISA::SyscallNumReg);
if (dynamic_cast<RiscvProcess64 *>(process))
syscallDescs64.get(num)->doSyscall(tc);
else

2
src/arch/riscv/process.cc
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@@ -244,7 +244,7 @@ RiscvProcess::argsInit(int pageSize)
}
ThreadContext *tc = system->threads[contextIds[0]];
tc->setIntReg(StackPointerReg, memState->getStackMin());
tc->setReg(StackPointerReg, memState->getStackMin());
tc->pcState(getStartPC());
memState->setStackMin(roundDown(memState->getStackMin(), pageSize));

84
src/arch/riscv/regs/int.hh
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@@ -49,27 +49,71 @@
#include <string>
#include <vector>
#include "cpu/reg_class.hh"
namespace gem5
{
namespace RiscvISA
{
const int NumIntArchRegs = 32;
const int NumMicroIntRegs = 1;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
namespace int_reg
{
// Semantically meaningful register indices
const int ReturnAddrReg = 1;
const int StackPointerReg = 2;
const int ThreadPointerReg = 4;
const int ReturnValueReg = 10;
const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
enum : RegIndex
{
_ZeroIdx, _RaIdx, _SpIdx, _GpIdx,
_TpIdx, _T0Idx, _T1Idx, _T2Idx,
_S0Idx, _S1Idx, _A0Idx, _A1Idx,
_A2Idx, _A3Idx, _A4Idx, _A5Idx,
_A6Idx, _A7Idx, _S2Idx, _S3Idx,
_S4Idx, _S5Idx, _S6Idx, _S7Idx,
_S8Idx, _S9Idx, _S10Idx, _S11Idx,
_T3Idx, _T4Idx, _T5Idx, _T6Idx,
const int SyscallNumReg = 17;
NumArchRegs,
const std::vector<std::string> IntRegNames = {
_Ureg0Idx = NumArchRegs,
NumRegs
};
inline constexpr RegId
Zero(IntRegClass, _ZeroIdx),
Ra(IntRegClass, _RaIdx),
Sp(IntRegClass, _SpIdx),
Gp(IntRegClass, _GpIdx),
Tp(IntRegClass, _TpIdx),
T0(IntRegClass, _T0Idx),
T1(IntRegClass, _T1Idx),
T2(IntRegClass, _T2Idx),
S0(IntRegClass, _S0Idx),
S1(IntRegClass, _S1Idx),
A0(IntRegClass, _A0Idx),
A1(IntRegClass, _A1Idx),
A2(IntRegClass, _A2Idx),
A3(IntRegClass, _A3Idx),
A4(IntRegClass, _A4Idx),
A5(IntRegClass, _A5Idx),
A6(IntRegClass, _A6Idx),
A7(IntRegClass, _A7Idx),
S2(IntRegClass, _S2Idx),
S3(IntRegClass, _S3Idx),
S4(IntRegClass, _S4Idx),
S5(IntRegClass, _S5Idx),
S6(IntRegClass, _S6Idx),
S7(IntRegClass, _S7Idx),
S8(IntRegClass, _S8Idx),
S9(IntRegClass, _S9Idx),
S10(IntRegClass, _S10Idx),
S11(IntRegClass, _S11Idx),
T3(IntRegClass, _T3Idx),
T4(IntRegClass, _T4Idx),
T5(IntRegClass, _T5Idx),
T6(IntRegClass, _T6Idx),
Ureg0(IntRegClass, _Ureg0Idx);
const std::vector<std::string> RegNames = {
"zero", "ra", "sp", "gp",
"tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1",
@@ -80,6 +124,22 @@ const std::vector<std::string> IntRegNames = {
"t3", "t4", "t5", "t6"
};
} // namespace int_reg
// Semantically meaningful register indices
inline constexpr auto
&ReturnAddrReg = int_reg::Ra,
&StackPointerReg = int_reg::Sp,
&ThreadPointerReg = int_reg::Tp,
&ReturnValueReg = int_reg::A0,
&AMOTempReg = int_reg::Ureg0,
&SyscallNumReg = int_reg::A7;
inline constexpr RegId ArgumentRegs[] = {
int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
int_reg::A4, int_reg::A5, int_reg::A6, int_reg::A7
};
} // namespace RiscvISA
} // namespace gem5

9
src/arch/riscv/remote_gdb.cc
View File

@@ -191,9 +191,8 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
// General registers
for (int i = 0; i < NumIntArchRegs; i++)
{
r.gpr[i] = context->readIntReg(i);
for (int i = 0; i < int_reg::NumArchRegs; i++) {
r.gpr[i] = context->getReg(RegId(IntRegClass, i));
}
r.pc = context->pcState().instAddr();
@@ -303,8 +302,8 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
RegVal newVal;
DPRINTF(GDBAcc, "setregs in remotegdb \n");
for (int i = 0; i < NumIntArchRegs; i++)
context->setIntReg(i, r.gpr[i]);
for (int i = 0; i < int_reg::NumArchRegs; i++)
context->setReg(RegId(IntRegClass, i), r.gpr[i]);
context->pcState(r.pc);
// Floating point registers

2
src/arch/riscv/remote_gdb.hh
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@@ -72,7 +72,7 @@ class RemoteGDB : public BaseRemoteGDB
*/
struct
{
uint64_t gpr[NumIntArchRegs];
uint64_t gpr[int_reg::NumArchRegs];
uint64_t pc;
uint64_t fpu[NumFloatRegs];
uint32_t fflags;

4
src/arch/riscv/se_workload.hh
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@@ -77,10 +77,10 @@ struct Result<RiscvISA::SEWorkload::SyscallABI, SyscallReturn>
{
if (ret.successful()) {
// no error
tc->setIntReg(RiscvISA::ReturnValueReg, ret.returnValue());
tc->setReg(RiscvISA::ReturnValueReg, ret.returnValue());
} else {
// got an error, return details
tc->setIntReg(RiscvISA::ReturnValueReg, ret.encodedValue());
tc->setReg(RiscvISA::ReturnValueReg, ret.encodedValue());
}
}
};

4
src/arch/riscv/utility.hh
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@@ -106,7 +106,7 @@ inline std::string
registerName(RegId reg)
{
if (reg.is(IntRegClass)) {
if (reg.index() >= NumIntArchRegs) {
if (reg.index() >= int_reg::NumArchRegs) {
/*
* This should only happen if a instruction is being speculatively
* executed along a not-taken branch, and if that instruction's
@@ -120,7 +120,7 @@ registerName(RegId reg)
str << "?? (x" << reg.index() << ')';
return str.str();
}
return IntRegNames[reg.index()];
return int_reg::RegNames[reg.index()];
} else {
if (reg.index() >= NumFloatRegs) {
std::stringstream str;