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arch-vega: Fix disassembly for two dword VOPC

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Calling opSelectorToRegSym in the disassembly for VOPC when there is a
second dword (SDWA, DPP, or Literal) causes a panic as those registers
do not have a string symbol. This is fixed by checking for a second
dword before printing similar to how VOP1, VOP2, SOP1, etc. function.

Change-Id: I97b33e1e45abcf3ff1d0bc5754773b4eee961a98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61269
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2022-07-11 16:05:38 -07:00
parent 616391e48a
commit 40077055cf
1 changed files with 8 additions and 1 deletions
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9
src/arch/amdgpu/vega/insts/op_encodings.cc
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@@ -906,7 +906,14 @@ namespace VegaISA
std::stringstream dis_stream;
dis_stream << _opcode << " vcc, ";
dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
if ((instData.SRC0 == REG_SRC_LITERAL) ||
(instData.SRC0 == REG_SRC_DPP) ||
(instData.SRC0 == REG_SRC_SWDA)) {
dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
<< _srcLiteral << ", ";
} else {
dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
}
dis_stream << "v" << instData.VSRC1;
disassembly = dis_stream.str();