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arch-sparc: Remove unused fixed register operands.

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These had been used to manually feed arguments to pseudoInsts (I think)
which is now handled automatically. Regardless, these are not used and
can be eliminated.

Change-Id: I1aeeb00627bbbfaaf550c878ee88b0b2f7f6b61d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49807
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-31 19:47:39 -07:00
parent 93fa99041d
commit a0e278863f
1 changed files with 0 additions and 9 deletions
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9
src/arch/sparc/isa/operands.isa
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@@ -142,16 +142,7 @@ def operands {{
'NNPC': PCStateOp('udw', 'nnpc',
(None, None, 'IsControl'), 30),
# Registers which are used explicitly in instructions
'R0': IntReg('udw', '0', None, 6),
'R1': IntReg('udw', '1', None, 7),
'R15': IntReg('udw', '15', 'IsInteger', 8),
'R16': IntReg('udw', '16', None, 9),
'O0': IntReg('udw', 'INTREG_O0', 'IsInteger', 10),
'O1': IntReg('udw', 'INTREG_O1', 'IsInteger', 11),
'O2': IntReg('udw', 'INTREG_O2', 'IsInteger', 12),
'O3': IntReg('udw', 'INTREG_O3', 'IsInteger', 13),
'O4': IntReg('udw', 'INTREG_O4', 'IsInteger', 14),
'O5': IntReg('udw', 'INTREG_O5', 'IsInteger', 15),
# Control registers
'Y': IntReg('udw', 'INTREG_Y', None, 40),