From a0e278863fcafc19ccd6fc0dfdab3ede608a601a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Aug 2021 19:47:39 -0700 Subject: [PATCH] arch-sparc: Remove unused fixed register operands. These had been used to manually feed arguments to pseudoInsts (I think) which is now handled automatically. Regardless, these are not used and can be eliminated. Change-Id: I1aeeb00627bbbfaaf550c878ee88b0b2f7f6b61d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49807 Maintainer: Gabe Black Reviewed-by: Boris Shingarov Tested-by: kokoro --- src/arch/sparc/isa/operands.isa | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 5e10017a5f..d85a81b28e 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -142,16 +142,7 @@ def operands {{ 'NNPC': PCStateOp('udw', 'nnpc', (None, None, 'IsControl'), 30), # Registers which are used explicitly in instructions - 'R0': IntReg('udw', '0', None, 6), - 'R1': IntReg('udw', '1', None, 7), 'R15': IntReg('udw', '15', 'IsInteger', 8), - 'R16': IntReg('udw', '16', None, 9), - 'O0': IntReg('udw', 'INTREG_O0', 'IsInteger', 10), - 'O1': IntReg('udw', 'INTREG_O1', 'IsInteger', 11), - 'O2': IntReg('udw', 'INTREG_O2', 'IsInteger', 12), - 'O3': IntReg('udw', 'INTREG_O3', 'IsInteger', 13), - 'O4': IntReg('udw', 'INTREG_O4', 'IsInteger', 14), - 'O5': IntReg('udw', 'INTREG_O5', 'IsInteger', 15), # Control registers 'Y': IntReg('udw', 'INTREG_Y', None, 40),