arch-vega,arch-gcn3: Add support for VCC_HI as scalar source

Currently there is only support for VCC_LO as a scalar source. Add
support for VCC_HI as well. The op selector symbol is also changed to be
vcc_hi/vcc_lo as it is in disassembly from LLVM.

Change-Id: I19ea8e23873049c33ffe2eb4ec8504a18f371c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61329
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2022-07-13 14:48:49 -07:00
parent 0fdfdbb130
commit af9ecf7920
4 changed files with 16 additions and 4 deletions

View File

@@ -654,7 +654,10 @@ namespace Gcn3ISA
ComputeUnit *cu = _gpuDynInst->computeUnit();
int sgprIdx(-1);
if (_opIdx == REG_VCC_LO) {
if (_opIdx == REG_VCC_HI) {
sgprIdx = cu->registerManager
->mapSgpr(wf, wf->reservedScalarRegs - 1 + dword);
} else if (_opIdx == REG_VCC_LO) {
sgprIdx = cu->registerManager
->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
} else if (_opIdx == REG_FLAT_SCRATCH_HI) {

View File

@@ -75,7 +75,10 @@ namespace Gcn3ISA
reg_sym = "flat_scratch_hi";
break;
case REG_VCC_LO:
reg_sym = "vcc";
reg_sym = "vcc_lo";
break;
case REG_VCC_HI:
reg_sym = "vcc_hi";
break;
case REG_M0:
reg_sym = "m0";

View File

@@ -644,7 +644,10 @@ namespace VegaISA
ComputeUnit *cu = _gpuDynInst->computeUnit();
int sgprIdx(-1);
if (_opIdx == REG_VCC_LO) {
if (_opIdx == REG_VCC_HI) {
sgprIdx = cu->registerManager
->mapSgpr(wf, wf->reservedScalarRegs - 1 + dword);
} else if (_opIdx == REG_VCC_LO) {
sgprIdx = cu->registerManager
->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
} else if (_opIdx == REG_FLAT_SCRATCH_HI) {

View File

@@ -75,7 +75,10 @@ namespace VegaISA
reg_sym = "flat_scratch_hi";
break;
case REG_VCC_LO:
reg_sym = "vcc";
reg_sym = "vcc_lo";
break;
case REG_VCC_HI:
reg_sym = "vcc_hi";
break;
case REG_M0:
reg_sym = "m0";