diff --git a/src/arch/amdgpu/gcn3/operand.hh b/src/arch/amdgpu/gcn3/operand.hh
index 6b51307f44..769f28a8a8 100644
--- a/src/arch/amdgpu/gcn3/operand.hh
+++ b/src/arch/amdgpu/gcn3/operand.hh
@@ -654,7 +654,10 @@ namespace Gcn3ISA
             ComputeUnit *cu = _gpuDynInst->computeUnit();
             int sgprIdx(-1);
 
-            if (_opIdx == REG_VCC_LO) {
+            if (_opIdx == REG_VCC_HI) {
+                sgprIdx = cu->registerManager
+                    ->mapSgpr(wf, wf->reservedScalarRegs - 1 + dword);
+            } else if (_opIdx == REG_VCC_LO) {
                 sgprIdx = cu->registerManager
                     ->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
             } else if (_opIdx == REG_FLAT_SCRATCH_HI) {
diff --git a/src/arch/amdgpu/gcn3/registers.cc b/src/arch/amdgpu/gcn3/registers.cc
index 3329cf1ff1..7f1d0dba37 100644
--- a/src/arch/amdgpu/gcn3/registers.cc
+++ b/src/arch/amdgpu/gcn3/registers.cc
@@ -75,7 +75,10 @@ namespace Gcn3ISA
             reg_sym = "flat_scratch_hi";
             break;
           case REG_VCC_LO:
-            reg_sym = "vcc";
+            reg_sym = "vcc_lo";
+            break;
+          case REG_VCC_HI:
+            reg_sym = "vcc_hi";
             break;
           case REG_M0:
             reg_sym = "m0";
diff --git a/src/arch/amdgpu/vega/operand.hh b/src/arch/amdgpu/vega/operand.hh
index d6542971ef..1760bd7213 100644
--- a/src/arch/amdgpu/vega/operand.hh
+++ b/src/arch/amdgpu/vega/operand.hh
@@ -644,7 +644,10 @@ namespace VegaISA
             ComputeUnit *cu = _gpuDynInst->computeUnit();
             int sgprIdx(-1);
 
-            if (_opIdx == REG_VCC_LO) {
+            if (_opIdx == REG_VCC_HI) {
+                sgprIdx = cu->registerManager
+                    ->mapSgpr(wf, wf->reservedScalarRegs - 1 + dword);
+            } else if (_opIdx == REG_VCC_LO) {
                 sgprIdx = cu->registerManager
                     ->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
             } else if (_opIdx == REG_FLAT_SCRATCH_HI) {
diff --git a/src/arch/amdgpu/vega/registers.cc b/src/arch/amdgpu/vega/registers.cc
index 2145ee38a5..b7404379cc 100644
--- a/src/arch/amdgpu/vega/registers.cc
+++ b/src/arch/amdgpu/vega/registers.cc
@@ -75,7 +75,10 @@ namespace VegaISA
             reg_sym = "flat_scratch_hi";
             break;
           case REG_VCC_LO:
-            reg_sym = "vcc";
+            reg_sym = "vcc_lo";
+            break;
+          case REG_VCC_HI:
+            reg_sym = "vcc_hi";
             break;
           case REG_M0:
             reg_sym = "m0";