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arch-arm: Overload decodeAArch64SysReg to accept a MiscRegNum64

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Overload decodeAArch64SysReg to directly accept a MiscRegNum64

Change-Id: I43c1dae6c0e382c03612f4ce4fc89aadddf30fd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61669
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-19 09:21:24 +01:00
parent ba5a017d9a
commit 6217ac737b
2 changed files with 9 additions and 1 deletions
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9
src/arch/arm/regs/misc.cc
View File

@@ -1297,12 +1297,19 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
unsigned op2)
{
MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
return decodeAArch64SysReg(sys_reg);
}
MiscRegIndex
decodeAArch64SysReg(const MiscRegNum64 &sys_reg)
{
auto it = miscRegNumToIdx.find(sys_reg);
if (it != miscRegNumToIdx.end()) {
return it->second;
} else {
// Check for a pseudo register before returning MISCREG_UNKNOWN
if ((op0 == 1 || op0 == 3) && (crn == 11 || crn == 15)) {
if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
(sys_reg.crn == 11 || sys_reg.crn == 15)) {
return MISCREG_IMPDEF_UNIMPL;
} else {
return MISCREG_UNKNOWN;

1
src/arch/arm/regs/misc.hh
View File

@@ -1259,6 +1259,7 @@ namespace ArmISA
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
unsigned crn, unsigned crm,
unsigned op2);
MiscRegIndex decodeAArch64SysReg(const MiscRegNum64 &misc_reg);
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg);
// Whether a particular AArch64 system register is -always- read only.