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cpu-o3: Remove TheISA:: types from forwardOldRegs.

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Use information from the registers' RegClass-es and the generic getReg
and setReg API to forward the registers value without having to refer to
the register class constant/index, or the type of complex registers.

Change-Id: I0426a606185edc0aabbf4b77c825b618b4640590
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50248
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-09-10 17:36:47 -07:00
parent 87acb97762
commit ba5a017d9a
1 changed files with 11 additions and 30 deletions
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41
src/cpu/o3/dyn_inst.hh
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@@ -1078,38 +1078,19 @@ class DynInst : public ExecContext, public RefCounted
for (int idx = 0; idx < numDestRegs(); idx++) {
PhysRegIdPtr prev_phys_reg = prevDestIdx(idx);
const RegId& original_dest_reg = staticInst->destRegIdx(idx);
switch (original_dest_reg.classValue()) {
case IntRegClass:
case FloatRegClass:
case CCRegClass:
const auto bytes = original_dest_reg.regClass().regBytes();
// Registers which aren't renamed don't need to be forwarded.
if (!original_dest_reg.isRenameable())
continue;
if (bytes == sizeof(RegVal)) {
setRegOperand(staticInst.get(), idx,
cpu->getReg(prev_phys_reg));
break;
case VecRegClass:
{
TheISA::VecRegContainer val;
cpu->getReg(prev_phys_reg, &val);
setRegOperand(staticInst.get(), idx, &val);
}
break;
case VecElemClass:
setRegOperand(staticInst.get(), idx,
cpu->getReg(prev_phys_reg));
break;
case VecPredRegClass:
{
TheISA::VecPredRegContainer val;
cpu->getReg(prev_phys_reg, &val);
setRegOperand(staticInst.get(), idx, &val);
}
break;
case InvalidRegClass:
case MiscRegClass:
// no need to forward misc reg values
break;
default:
panic("Unknown register class: %d",
(int)original_dest_reg.classValue());
} else {
uint8_t val[original_dest_reg.regClass().regBytes()];
cpu->getReg(prev_phys_reg, val);
setRegOperand(staticInst.get(), idx, val);
}
}
}