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cpu-minor: Use the << operator in minorTraceInst.

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Use that to print the RegIds of an inst directly, without having to pass
around the register class vector.

Change-Id: I6e5b06518f4826a1e4e8589c5ed095609d3d02b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49809
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
Maintainer: ZHENGRONG WANG <seanyukigeek@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-31 06:18:31 -07:00
parent a46b7c99c8
commit 87acb97762
4 changed files with 10 additions and 19 deletions
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17
src/cpu/minor/dyn_inst.cc
View File

@@ -134,10 +134,8 @@ operator <<(std::ostream &os, const MinorDynInst &inst)
/** Print a register in the form r<n>, f<n>, m<n>(<name>) for integer,
* float, and misc given an 'architectural register number' */
static void
printRegName(std::ostream &os, const RegId& reg,
const BaseISA::RegClasses &reg_classes)
printRegName(std::ostream &os, const RegId& reg)
{
const auto &reg_class = *reg_classes.at(reg.classValue());
switch (reg.classValue()) {
case InvalidRegClass:
os << 'z';
@@ -145,7 +143,7 @@ printRegName(std::ostream &os, const RegId& reg,
case MiscRegClass:
{
RegIndex misc_reg = reg.index();
os << 'm' << misc_reg << '(' << reg_class.regName(reg) << ')';
os << 'm' << misc_reg << '(' << reg << ')';
}
break;
case FloatRegClass:
@@ -155,7 +153,7 @@ printRegName(std::ostream &os, const RegId& reg,
os << 'v' << reg.index();
break;
case VecElemClass:
os << reg_class.regName(reg);
os << reg;
break;
case IntRegClass:
os << 'r' << reg.index();
@@ -169,8 +167,7 @@ printRegName(std::ostream &os, const RegId& reg,
}
void
MinorDynInst::minorTraceInst(const Named &named_object,
const BaseISA::RegClasses &reg_classes) const
MinorDynInst::minorTraceInst(const Named &named_object) const
{
if (isFault()) {
minorInst(named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
@@ -188,8 +185,7 @@ MinorDynInst::minorTraceInst(const Named &named_object,
unsigned int src_reg = 0;
while (src_reg < num_src_regs) {
printRegName(regs_str, staticInst->srcRegIdx(src_reg),
reg_classes);
printRegName(regs_str, staticInst->srcRegIdx(src_reg));
src_reg++;
if (src_reg != num_src_regs)
@@ -200,8 +196,7 @@ MinorDynInst::minorTraceInst(const Named &named_object,
unsigned int dest_reg = 0;
while (dest_reg < num_dest_regs) {
printRegName(regs_str, staticInst->destRegIdx(dest_reg),
reg_classes);
printRegName(regs_str, staticInst->destRegIdx(dest_reg));
dest_reg++;
if (dest_reg != num_dest_regs)

3
src/cpu/minor/dyn_inst.hh
View File

@@ -269,8 +269,7 @@ class MinorDynInst : public RefCounted
/** Print (possibly verbose) instruction information for
* MinorTrace using the given Named object's name */
void minorTraceInst(const Named &named_object,
const BaseISA::RegClasses &reg_classes) const;
void minorTraceInst(const Named &named_object) const;
/** ReportIF interface */
void reportData(std::ostream &os) const;

3
src/cpu/minor/execute.cc
View File

@@ -783,8 +783,7 @@ Execute::issue(ThreadID thread_id)
/* Generate MinorTrace's MinorInst lines. Do this at commit
* to allow better instruction annotation? */
if (debug::MinorTrace && !inst->isBubble()) {
inst->minorTraceInst(*this,
cpu.threads[0]->getIsaPtr()->regClasses());
inst->minorTraceInst(*this);
}
/* Mark up barriers in the LSQ */

6
src/cpu/minor/fetch2.cc
View File

@@ -486,10 +486,8 @@ Fetch2::evaluate()
/* Output MinorTrace instruction info for
* pre-microop decomposition macroops */
if (debug::MinorTrace && !dyn_inst->isFault() &&
dyn_inst->staticInst->isMacroop())
{
dyn_inst->minorTraceInst(*this,
cpu.threads[0]->getIsaPtr()->regClasses());
dyn_inst->staticInst->isMacroop()) {
dyn_inst->minorTraceInst(*this);
}
}