diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 133411b144..e5cf50cca0 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1297,12 +1297,19 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
                     unsigned op2)
 {
     MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
+    return decodeAArch64SysReg(sys_reg);
+}
+
+MiscRegIndex
+decodeAArch64SysReg(const MiscRegNum64 &sys_reg)
+{
     auto it = miscRegNumToIdx.find(sys_reg);
     if (it != miscRegNumToIdx.end()) {
         return it->second;
     } else {
         // Check for a pseudo register before returning MISCREG_UNKNOWN
-        if ((op0 == 1 || op0 == 3) && (crn == 11 || crn == 15)) {
+        if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
+            (sys_reg.crn == 11 || sys_reg.crn == 15)) {
             return MISCREG_IMPDEF_UNIMPL;
         } else {
             return MISCREG_UNKNOWN;
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 141b3aad50..e9a83c4628 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1259,6 +1259,7 @@ namespace ArmISA
     MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
                                      unsigned crn, unsigned crm,
                                      unsigned op2);
+    MiscRegIndex decodeAArch64SysReg(const MiscRegNum64 &misc_reg);
     MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg);
 
     // Whether a particular AArch64 system register is -always- read only.