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arch-vega: implement S_GETREG_B32 instruction

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This commit adds support for the Vega GPU ISA's S_GETREG_B32
instruction.

This work was done by Charles Jamieson but I am committing.

Change-Id: Ic2e24f667ed1aec7b8b1404a06e17e7ffb192fba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60589
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Charles Jamieson
2022-06-16 12:43:47 -05:00
committed by Matt Sinclair
parent 508c1cf69a
commit 7170c365be
1 changed files with 15 additions and 1 deletions
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16
src/arch/amdgpu/vega/insts/instructions.cc
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@@ -2017,6 +2017,7 @@ namespace VegaISA
Inst_SOPK__S_GETREG_B32::Inst_SOPK__S_GETREG_B32(InFmt_SOPK *iFmt)
: Inst_SOPK(iFmt, "s_getreg_b32")
{
setFlag(ALU);
} // Inst_SOPK__S_GETREG_B32
Inst_SOPK__S_GETREG_B32::~Inst_SOPK__S_GETREG_B32()
@@ -2031,7 +2032,20 @@ namespace VegaISA
void
Inst_SOPK__S_GETREG_B32::execute(GPUDynInstPtr gpuDynInst)
{
panicUnimplemented();
ScalarRegI16 simm16 = instData.SIMM16;
ScalarRegU32 hwregId = simm16 & 0x3f;
ScalarRegU32 offset = (simm16 >> 6) & 31;
ScalarRegU32 size = ((simm16 >> 11) & 31) + 1;
ScalarOperandU32 hwreg(gpuDynInst, hwregId);
ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
hwreg.read();
sdst.read();
// Store value from hardware to part of the SDST.
ScalarRegU32 mask = (((1U << size) - 1U) << offset);
sdst = (hwreg.rawData() & ~mask);
sdst.write();
} // execute
// --- Inst_SOPK__S_SETREG_B32 class methods ---