Commit Graph

445 Commits

Author SHA1 Message Date
Gabe Black
b3365e767a arch: Make the ISA::clear() method virtual.
This method is not at all on the critical path, and the adding virtual
method overhead to it will have essentially no effect on over all
performance.

Change-Id: I583bbe30f5ed923a0c771f36c3f07e5979c28476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51236
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-20 01:14:54 +00:00
Gabe Black
d130fdc092 arch: Remove unused register flattening methods.
Most flattening methods in the ISA classes aren't used. The one
exception is the flattenMiscIndex function in ARM.

Change-Id: I26088692fe3f56914009afb0203f59da7cf6023a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51235
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-08-20 01:14:36 +00:00
Gabe Black
244f80dde1 arch: Eliminate the vecregs.hh switching header file.
Delete the headers that are in each arch, and remove it from the list of
switching header files in arch/SConscript.

Change-Id: Ic0089f83e83f76ad6308ecfb5007b5ef11e1d949
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50256
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-04 20:22:59 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-03 09:10:41 +00:00
Gabe Black
e425bcabd2 arch,cpu,sim: Store registers in InstRecord with InstResult.
The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-08-02 12:44:25 +00:00
Gabe Black
cc4380b0d6 cpu,arch: Put the name of the RegClass into the RegClass.
Move the name of the RegClass out of constants which belong to the
RegId, and instead store them in the RegClass instances.

Change-Id: I1ddd4bc8467d5e3f178db7a11c8f8052f43fd7ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-07-29 19:30:51 +00:00
Gabe Black
654451c2be arch,cpu: Keep a RegClass pointer in RegId instead of a RegClassType.
This makes it easy to get access to the RegClass that goes with a
register without having to look it up in a separate structure.

Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49786
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 13:54:32 +00:00
Gabe Black
45cf2e3c34 arch: Minimize use of RegClassType constants and the RegId constructor.
These are global values which prevent making register types ISA
specific.

Change-Id: I513adcae5ad316122c24f25a9e01b9974629510f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49785
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-27 10:59:07 +00:00
Gabe Black
70289e72cd arch,cpu: Store pointers to RegClass-es instead of instances.
This lets us put the actual RegClass-es somewhere else and give them
names.

Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49784
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
2022-07-26 19:37:59 +00:00
Gabe Black
85a18e22a1 arch,cpu: Keep track of the RegClassType of a RegClass.
This makes it possible to do more things with a RegClass locally.

Change-Id: Ib7d7fa3e2d88a34d5b5681fcc4aab26696c71205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49779
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-06-24 11:27:23 +00:00
Gabe Black
6a73a3a2d0 arch: Switch the generic register ABI over to use RegId.
Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49774
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-06-19 07:48:14 +00:00
Gabe Black
0d18112f0f arch-power: Revamp float regs.
Change-Id: I77a5a021da82c8528d092f7363a927dec224d5ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49771
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-08 20:35:16 +00:00
Gabe Black
23087f124a arch-power: Revamp int registers.
Change-Id: I2e11601a6bf37d6ca161d0ce99d7bfff1ee2f0eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49770
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-06-08 20:35:01 +00:00
Gabe Black
a40950a5c9 arch,cpu: Remove the idea of a zero register.
This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-07 18:26:33 +00:00
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict.
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 20:31:21 +00:00
Gabe Black
abdf573c53 arch-power: Use the OperandDesc classes in the ISA description.
Change-Id: I7c46d97f581cd114dcdc8061fa555d5ac927aa2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49730
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-11 08:37:42 +00:00
Gabe Black
64171d4d14 cpu,arch: Attach a debug flag to each RegClass.
This can be used for DPRINTFs related to those registers using DPRINTFV.

Change-Id: I0fccb12b70fdb74e01022fe0d3d9c2f92425a5bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49696
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-02-24 00:10:17 +00:00
Gabe Black
5e1fdf7586 arch: Remove TheISA::VecElem from arch/vecregs.hh.
Also remove unnecessary includes from the x86 version, and fix up
transitive includes from other x86 files.

Change-Id: I9f7d330f287c9ed52eed1544c47251b4354cfab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49166
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 18:48:55 +00:00
Gabe Black
f4ee1a9536 arch: Get rid of the TheISA::NumVecElemPerVecReg variable.
Remove it from the arch/vecregs.hh interface. It's used internally by
ARM, where it will remain.

Change-Id: Ic319b404cbd77875c780faee66d5abdd7bfc0608
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49165
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 18:48:18 +00:00
Gabe Black
c498d8bced cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
The BaseCPU type had been specializing itself based on the value of
TARGET_ISA, which is not compatible with building more than one ISA at a
time.

This change refactors the CPU models so that the BaseCPU is more
general, and the ISA specific components are added to the CPU when the
CPU types are fully specialized. For instance, The AtomicSimpleCPU has a
version called X86AtomicSimpleCPU which installs the X86 specific
aspects of the CPU.

This specialization is done in three ways.

1. The mmu parameter is assigned an instance of the architecture
specific MMU type. This provides a reasonable default, but also avoids
having having to use the ISA specific type when the parameter is
created.

2. The ISA specific types are made available as class attributes, and
the utility functions (including __init__!) in the BaseCPU class can
refer to them to get the types they need to set up the CPU at run time.

Because SimObjects have strange, unhelpful semantics as far as assigning
to their attributes, these types need to be set up in a non-SimObject
class, which is then brought in as a base of the actual SimObject type.
Because the metaclass of this other type is just "type", things work
like you would expect. The SimObject doesn't do any special processing
of base classes if they aren't also SimObjects, so these attributes
survive and are accessible using normal lookup in the BaseCPU class.

3. There are some methods like addCheckerCPU and properties like
needsTSO which have ISA specific values or behaviors. These are set in
the ISA specific subclass, where they are inherently specific to an ISA
and don't need to check TARGET_ISA.

Also, the DummyChecker which was set up for the BaseSimpleCPU which
doesn't actually do anything in either C++ or python was not carried
forward. The CPU type still exists, but it isn't installed in the
simple CPUs.

To provide backward compatibility, each ISA implements a .py file which
matches the original .py for a CPU, and the original is renamed with a
Base prefix. The ISA specific version creates an alias with the old CPU
name which maps to the ISA specific type. This way, old scripts which
refer to, for example, AtomicSimpleCPU, will get the X86AtomicSimpleCPU
if the x86 version was compiled in, the ArmAtomicSimpleCPU on arm, etc.

Unfortunately, because of how tags on PySource and by extension SimObjects
are implemented right now, if you set the tags on two SimObjects or
PySources which have the same module path, the later will overwrite the
former whether or not they both would be included. There are some
changes in review which would revamp this and make it work like you
would expect, without this central bookkeeping which has the conflict.
Since I can't use that here, I fell back to checking TARGET_ISA to
decide whether to tell SCons about those files at all.

In the long term, this mechanism should be revamped so that these
compatibility types are only available if there is exactly one ISA
compiled into gem5. After the configs have been updated and no longer
assume they can use AtomicSimpleCPU in all cases, then these types can
be deleted.

Also, because ISAs can now either provide subclasses for a CPU or not,
the CPU_MODELS variable has been removed, meaning the non-ISA
specialized versions of those CPU models will always be included in
gem5, except when building the NULL ISA.

In the future, a more granular config mechanism will hopefully be
implemented for *all* of gem5 and not just the CPUs, and these can be
conditional again in case you only need certain models, and want to
reduce build time or binary size by excluding the others.

Change-Id: I02fc3f645c551678ede46268bbea9f66c3f6c74b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-12 15:59:27 +00:00
Gabe Black
2be95c4470 arch,sim-se: Handle syscall retry/suppression in the syscall desc.
Rather than make each ISA include boilerplate to ignore a
SyscallReturn's value when it's marked as suppressed or needing a retry,
put that code into the SyscallDesc::doSyscall method instead.

That has two benefits. First, it removes a decent amount of code
duplication which is nice from a maintenance perspective. Second, it
puts the SyscallDesc in charge of figuring out what to do once a system
call implementation finishes. That will let it schedule a retry of the
system call for instance, without worrying about what the ISA is doing
with the SyscallReturn behind its back.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1123

Change-Id: I3732a98c8e0d0b2b94d61313960aa0782c0b971f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54023
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-12-13 20:31:51 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject().
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
Gabe Black
25d36c81c9 arch,cpu: Turn the Decoder objects into SimObjects.
Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
3d52a0ea97 arch: Make the decoder decode() method virtual.
Change-Id: I60f0c4ffbd63069caaee190a78f007df79b61808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52078
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
ce60dc8d3a arch: Make the decoder moreBytes method virtual.
Change-Id: I9135508916de91172ec9649d59d80574ac2aaf16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52077
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
792745f4f0 arch: Make the decoder takeOverFrom method virtual.
This is only implemented for x86. It's called very rarely, and so
virtual function overhead is practically irrelevant.

Change-Id: Ib6e05a903df95b801164e44d1662e130419fdbd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52076
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
b65272e7f1 arch: Remove "process()" from the Decoder interface.
This method was only ever an implementation detail on ARM and x86, the
only places it actually did anything. Remove it from the other decoders,
and also make it protected on x86 to remove confusion.

Change-Id: I3a719648039c1edfbc2bd044f0a21c8983b249f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
81fa62fc91 arch: Make the decoder reset() method virtual.
This is called very infrequently, and so it's virtual overhead is
practically irrelevant.

Change-Id: If92cd96f75234c65c4cdffe392c32cfdd9b0c8cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52074
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
5e7c964158 arch: Promote outOfBytes/needMoreBytes to the InstDecoder class.
Change-Id: Ie8f31e424081f002e3d74edd1685b4a977c545c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52073
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
29950b81ce arch: Promote instReady to the base InstDecoder class.
Move the instDone flag, and the instReady function which was
consistently implemented just to return it, to the base InstDecoder
class. This flag can still be accessed easily from the subclasses, but
now it can be retrieved with just an InstDecoder pointer without a
virtual function call.

Change-Id: I8c662aa01da8fe33ffe679071c701e0aadc1a795
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52072
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
21d7ae9508 arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs.
Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:05:41 +00:00
Gabe Black
2805f3dee1 misc: Stop including arch/pcstate.hh.
Change-Id: Ic9ea62ae9c59fd838175fd6af4c075101d46a0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52067
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
e75ae455ad arch,cpu: Use PCStateBase for decoder methods.
Change-Id: I79f1c5dd39de7015a5c5b891e1888d9a176bb5b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52063
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
8279191cd9 misc,cpu: Make ThreadContext work with PCStateBase-s.
Change-Id: I92f1d79c697bb45f610604c9e84b24ea93d58776
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52058
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-30 23:30:06 +00:00
Gabe Black
39584edc72 arch,cpu: Convert ExecContext::pcState to use PCStateBase.
Some places need persistent temporaries for the return values of
ThreadContext::pcState(), which is currently by value.

Change-Id: Icd4924f1d16ebe1c99c54ed47616733422340cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52057
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-29 22:00:54 +00:00
Gabe Black
ecd3cc85f0 arch,cpu: Use PCStateBase in StaticInst::branchTarget
Change-Id: I1b8a2ea088b52252601968b1b1083ed712a5bfd6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52045
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
9d48180e4a arch,cpu: Use PCStateBase in buildRetPC.
Change-Id: I9d9f5b25613440737b1d67134fcae09aa68baf8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52044
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
5ad4cf0af1 arch,cpu,sim: Use PCStateBase in advancePC.
By using a PCStateBase pointer or reference, we can (mostly) avoid
having to know what the ISA specific PState class is, letting the ISA
specific instruction classes cast to the type they need internally.

There are a couple minor places where we need to do those casts outside
of ISA specific types, one in the generic NopStaticInstPtr class, and a
few in generic faults.

Right now, we'll just use the TheISA::PCState type in those isolated
spots (sometimes hidden by auto), and deal with it later, possibly
with a virtual "advance" method of some sort.

Change-Id: I774c67dc648a85556230f601e087211b3d5630a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52043
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
f784097f7a arch: Add a "set" function to set one PCState to another.
Most of the time, the type pointed to by a PCState pointer or reference
will be the same as all the others, if not nullptr.

This change adds a set of "set" functions which assume that the
underlying type of each pointer or reference are the same, and handles
casting, copying things over, creating a new copy, etc, for you. It uses
a new "update" virtual method on PCState subclasses which casts the
source to the same type as the destination and copies values over.

Note that the "set" function doesn't actually verify that the two types
are the same, just like the overloaded ==, != and << operators. In the
future, those checks can be added for debugging purposes, probably
guarded by a configuration variable which can be toggled on or off to
get better performance or more thorough error checking.

The main advantage of these wrappers are that they allows consistent
semantics whether your moving a value from a pointer, or from a yet
unconverted PCState subclass, or vice versa, which will be particularly
helpful while transitioning between using raw PCState instances and
using primarily pointers and references.

This change also adds wrappers which handle std::unique_ptr, which makes
it easier to use them as arguments to these functions. Otherwise, if the
std::unique_ptr is a temporary value, using the return value of .get()
will let the std::unique_ptr go out of scope, making it delete the data
pointed to by the returned pointed. By keeping the std::unique_ptr
around on the stack, that prevents it from going out of scope.

Change-Id: I2c737b08e0590a2c46e212a7b9efa543bdb81ad3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52041
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
Gabe Black
3ecc9f8b66 arch: Add a newPCState method to the ISA class.
This method is the seed which creates a new PCState object of the
appropriate type. It can be used to initialize PCStateBase *s so that they
always point to something valid and can be manipulated without having to
first check if there's something there, as opposed to the alternative
where a pointer might be null until it's first pointed at something.

Change-Id: If06ee633846603acbfd2432f3d8bac6746a8b729
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-23 07:45:29 +00:00
Gabe Black
5e3226bed5 arch,sim: Add a byteOrder accessor to the Workload class.
The workload would have a better idea of what it's endianness is than
the system object that holds it. This is the first step towards getting
rid of the getByteOrder method on the system object, which currently
checks TARGET_ISA to determine what the default endianness should be.

If it makes sense for a Workload, it could determine the endianness
dynamically by, for instance, reading it out of a binary image before
putting it into memory.

This does assume that the workload has a consistent endianness
throughout which may not be true, but this is not a new assumption.

Also, mark the SEWorkload SimObject class as "abstract", since it isn't
useful until they get subclassed by some arch specific version.

Change-Id: I8d4ba8382f22236a81f9738cc3506cdb97bdbfb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52104
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-18 07:09:00 +00:00
Gabe Black
4b361aa4bc arch,cpu: Refactor PCState construction a little.
Make the Addr constructor explicit to avoid implicit/hidden conversions
from Addr.

Also, add a copy constructor to the PCState types, and explicitly enable
the assignment operator.

Change-Id: Ibef17ece7fd06b2f9709c46d118e88a80da0b194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52036
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
3f937352fa arch: Add a virtual clone() method to PCState.
This will let callers create a separate copy of a PCState class
instance. This makes it more explicit when creating copies of a PCState
to make sure the programmer is more aware, and avoids having to know
what the actual type is to make a copy.

Change-Id: I728a278afdb55b800c753a5b7f65f62f4a80c043
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52035
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
25138cbb7a arch: Simplify and tidy up PCState classes.
Change-Id: Ife5412fdd8cc8093371365b8dd4705f77b952191
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52034
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-10-28 05:50:26 +00:00
Gabe Black
fbe002bf12 arch: Make the MMU ranged translateFunction pure virtual.
The (simple) implementation in each ISAs MMU can then specify the page
size it wants, which is the page size appropriate for that ISA.

Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50761
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-10-22 21:43:02 +00:00
Gabe Black
73025695c7 scons: Use tags to gate ISA files and not env['TARGET_ISA'].
Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50336
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-19 20:41:03 +00:00
Gabe Black
1ee4c4ce43 arch-power: Replace the Loader namespace with loader.
The Loader namespace is deprecated, and is replaced with loader.

Change-Id: Ic973eefd55c6f8a43d3d41346b8b6e4795e19e55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51527
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:29:08 +00:00
Giacomo Travaglini
851e543b2f misc: Using OS::off_t in syscall signature
Change-Id: Iefa1e207a3e825959b0fe8df30e6be182d73a0f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51490
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Giacomo Travaglini
37495f8823 misc: Using OS::size_t in syscall signature
Using the host size_t is confusing the guest ABI engine every time
the host and the guest adopt a different data model (ILP32 vs LP64)

For example when a LP64 machine is running an ILP32 application in SE
mode, "size_t" will wrongly inform the guest ABI engine to retrieve the
argument by loading a 64 bit (instead of 32) value from the stack

JIRA: https://gem5.atlassian.net/browse/GEM5-1074

Change-Id: Id7d7740ac429f534a4089331bedf21dc3951bbad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Gabe Black
1a1ba692c3 sim: Move the MemPools object out of System and into SEWorkload.
This removes the need for all the FullSystem checks in the System class,
and simplifies that class in general.

Change-Id: Ie8a3bc67db9195027d2111009b15ca59221bdeb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50348
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-30 00:30:49 +00:00