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e425bcabd29caabf37efa2148653a329e2c00a63
gem5/src/arch/power
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Gabe Black e425bcabd2 arch,cpu,sim: Store registers in InstRecord with InstResult. 
The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-08-02 12:44:25 +00:00
..
gdb-xml
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
insts
arch-power: Revamp int registers.
2022-06-08 20:35:01 +00:00
isa
arch,cpu,sim: Store registers in InstRecord with InstResult.
2022-08-02 12:44:25 +00:00
linux
arch-power: Revamp int registers.
2022-06-08 20:35:01 +00:00
regs
cpu,arch: Put the name of the RegClass into the RegClass.
2022-07-29 19:30:51 +00:00
AtomicSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decoder.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.hh
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
faults.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
faults.hh
arch-power: Add support for trapping user faults
2021-07-04 18:19:56 +00:00
interrupts.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa.cc
cpu,arch: Put the name of the RegClass into the RegClass.
2022-07-29 19:30:51 +00:00
isa.hh
arch: Add a newPCState method to the ISA class.
2021-11-23 07:45:29 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
NonCachingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
page_size.hh
arch-power: Update copyrights
2021-07-04 18:20:26 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch: Add a "set" function to set one PCState to another.
2021-11-23 07:45:29 +00:00
PowerCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
PowerDecoder.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
PowerInterrupts.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PowerISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PowerMMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
PowerSeWorkload.py
arch-power: Add multi-mode support
2021-07-04 18:19:19 +00:00
PowerTLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
arch: Minimize use of RegClassType constants and the RegId constructor.
2022-07-27 10:59:07 +00:00
process.hh
arch-power: Update copyrights
2021-07-04 18:20:26 +00:00
remote_gdb.cc
arch: Minimize use of RegClassType constants and the RegId constructor.
2022-07-27 10:59:07 +00:00
remote_gdb.hh
arch-power: Revamp float regs.
2022-06-08 20:35:16 +00:00
SConscript
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.cc
arch: Switch the generic register ABI over to use RegId.
2022-06-19 07:48:14 +00:00
se_workload.hh
arch: Switch the generic register ABI over to use RegId.
2022-06-19 07:48:14 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
tlb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
tlb.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
types.hh
arch-power: Update copyrights
2021-07-04 18:20:26 +00:00
vecregs.hh
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00