arch: Add TypeTLB Param in BaseTLB

This patch is adding an enum Param in the BaseTLB to tag which kind of
translation entries the TLB is holding

* instruction: holding instruction entries
* data: holding data entries
* unified: holding instruction and data entries

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I033f840652f354523f48e9eb78033ea759b5d0e0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48142
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/ArmMMU.py

@@ -67,8 +67,12 @@ class ArmMMU(BaseMMU):
 
     sys = Param.System(Parent.any, "system object parameter")
 
-    stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB")
-    stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB")
+    stage2_itb = Param.ArmTLB(
+        ArmStage2TLB(entry_type="instruction"),
+        "Stage 2 Instruction TLB")
+    stage2_dtb = Param.ArmTLB(
+        ArmStage2TLB(entry_type="data"),
+        "Stage 2 Data TLB")
 
     itb_walker = Param.ArmTableWalker(
         ArmTableWalker(), "HW Table walker")

src/arch/arm/ArmTLB.py

@@ -53,7 +53,7 @@ class ArmStage2TLB(ArmTLB):
     is_stage2 = True
 
 class ArmITB(ArmTLB):
-    pass
+    entry_type = "instruction"
 
 class ArmDTB(ArmTLB):
-    pass
+    entry_type = "data"

src/arch/arm/fastmodel/iris/Iris.py

@@ -53,8 +53,8 @@ class IrisMMU(BaseMMU):
     type = 'IrisMMU'
     cxx_class = 'gem5::Iris::MMU'
     cxx_header = 'arch/arm/fastmodel/iris/mmu.hh'
-    itb = IrisTLB()
-    dtb = IrisTLB()
+    itb = IrisTLB(entry_type="instruction")
+    dtb = IrisTLB(entry_type="data")
 
 class IrisInterrupts(BaseInterrupts):
     type = 'IrisInterrupts'

src/arch/generic/BaseTLB.py

@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2008 The Hewlett-Packard Development Company
 # Copyright (c) 2018 Metempsy Technology Consulting
 # All rights reserved.
@@ -28,6 +40,18 @@
 from m5.params import *
 from m5.SimObject import SimObject
 
+class TypeTLB(ScopedEnum):
+    """
+    instruction: TLB contains instruction entries only
+    data: TLB contains data entries only
+    unified: TLB contains both instruction and data entries
+    """
+    map = {
+        'instruction' : 0x1,
+        'data' : 0x2,
+        'unified' : 0x3,
+    }
+
 class BaseTLB(SimObject):
     type = 'BaseTLB'
     abstract = True
@@ -41,3 +65,5 @@ class BaseTLB(SimObject):
     mem_side_port = RequestPort("Port closer to memory side")
     master   = DeprecatedParam(mem_side_port,
                     '`master` is now called `mem_side_port`')
+
+    entry_type = Param.TypeTLB("Instruction/Data/Unified TLB entries")

src/arch/generic/tlb.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011, 2021 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -43,7 +43,9 @@
 
 #include "arch/generic/mmu.hh"
 #include "base/logging.hh"
+#include "enums/TypeTLB.hh"
 #include "mem/request.hh"
+#include "params/BaseTLB.hh"
 #include "sim/sim_object.hh"
 
 namespace gem5
@@ -54,7 +56,11 @@ class ThreadContext;
 class BaseTLB : public SimObject
 {
   protected:
-    BaseTLB(const Params &p) : SimObject(p) {}
+    BaseTLB(const BaseTLBParams &p)
+      : SimObject(p), _type(p.entry_type)
+    {}
+
+    TypeTLB _type;
 
   public:
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
@@ -111,6 +117,8 @@ class BaseTLB : public SimObject
     virtual Port* getTableWalkerPort() { return NULL; }
 
     void memInvalidate() { flushAll(); }
+
+    TypeTLB type() const { return _type; }
 };
 
 } // namespace gem5

src/arch/mips/MipsMMU.py

@@ -42,5 +42,5 @@ class MipsMMU(BaseMMU):
     type = 'MipsMMU'
     cxx_class = 'gem5::MipsISA::MMU'
     cxx_header = 'arch/mips/mmu.hh'
-    itb = MipsTLB()
-    dtb = MipsTLB()
+    itb = MipsTLB(entry_type="instruction")
+    dtb = MipsTLB(entry_type="data")

src/arch/power/PowerMMU.py

@@ -42,5 +42,5 @@ class PowerMMU(BaseMMU):
     type = 'PowerMMU'
     cxx_class = 'gem5::PowerISA::MMU'
     cxx_header = 'arch/power/mmu.hh'
-    itb = PowerTLB()
-    dtb = PowerTLB()
+    itb = PowerTLB(entry_type="instruction")
+    dtb = PowerTLB(entry_type="data")

src/arch/riscv/RiscvMMU.py

@@ -47,8 +47,8 @@ class RiscvMMU(BaseMMU):
     cxx_class = 'gem5::RiscvISA::MMU'
     cxx_header = 'arch/riscv/mmu.hh'
 
-    itb = RiscvTLB()
-    dtb = RiscvTLB()
+    itb = RiscvTLB(entry_type="instruction")
+    dtb = RiscvTLB(entry_type="data")
     pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
     pmp = Param.PMP(PMP(), "Physical Memory Protection Unit")
 

src/arch/sparc/SparcMMU.py

@@ -44,5 +44,5 @@ class SparcMMU(BaseMMU):
     type = 'SparcMMU'
     cxx_class = 'gem5::SparcISA::MMU'
     cxx_header = 'arch/sparc/mmu.hh'
-    itb = SparcTLB()
-    dtb = SparcTLB()
+    itb = SparcTLB(entry_type="instruction")
+    dtb = SparcTLB(entry_type="data")

src/arch/x86/X86MMU.py

@@ -42,8 +42,8 @@ class X86MMU(BaseMMU):
     type = 'X86MMU'
     cxx_class = 'gem5::X86ISA::MMU'
     cxx_header = 'arch/x86/mmu.hh'
-    itb = X86TLB()
-    dtb = X86TLB()
+    itb = X86TLB(entry_type="instruction")
+    dtb = X86TLB(entry_type="data")
 
     @classmethod
     def walkerPorts(cls):